---

yaml --- r: 226204 b: refs/heads/master c: 301c9f2 h: refs/heads/master v: v3
git-mirror · Dec 29, 2010 · d078299 · d078299
1 parent 650b3db
commit d078299
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Showing 3 changed files with 15 additions and 5 deletions.
diff --git a/[refs] b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: d2c194ce4781d62bf671aa6b65a2fccb39feb50e
+refs/heads/master: 301c9f26d7ded6e274a99c3a447a9a36790a3f3e
diff --git a/trunk/drivers/media/dvb/frontends/au8522_decoder.c b/trunk/drivers/media/dvb/frontends/au8522_decoder.c
@@ -278,10 +278,18 @@ static void setup_decoder_defaults(struct au8522_state *state, u8 input_mode)
 			AU8522_TVDEC_COMB_HDIF_THR2_REG06AH_CVBS);
 	au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR3_REG06BH,
 			AU8522_TVDEC_COMB_HDIF_THR3_REG06BH_CVBS);
-	au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH,
-			AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_CVBS);
-	au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH,
-			AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_CVBS);
+	if (input_mode == AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH13 ||
+	    input_mode == AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH24) {
+		au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH,
+				AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_SVIDEO);
+		au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH,
+				AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_SVIDEO);
+	} else {
+		au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH,
+				AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_CVBS);
+		au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH,
+				AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_CVBS);
+	}
 	au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH,
 			AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH_CVBS);
 	au8522_writereg(state, AU8522_TVDEC_UV_SEP_THR_REG06FH,

diff --git a/trunk/drivers/media/dvb/frontends/au8522_priv.h b/trunk/drivers/media/dvb/frontends/au8522_priv.h
@@ -397,7 +397,9 @@ void au8522_release_state(struct au8522_state *state);
 #define AU8522_TVDEC_COMB_HDIF_THR2_REG06AH_CVBS		0x0A
 #define AU8522_TVDEC_COMB_HDIF_THR3_REG06BH_CVBS		0x32
 #define AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_CVBS		0x34
+#define AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_SVIDEO		0x2a
 #define AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_CVBS		0x05
+#define AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_SVIDEO		0x15
 #define AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH_CVBS		0x6E
 #define AU8522_TVDEC_UV_SEP_THR_REG06FH_CVBS			0x0F
 #define AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H_CVBS		0x80