---

yaml --- r: 221669 b: refs/heads/master c: 5aefa34 h: refs/heads/master i: 221667: 341c6fd v: v3
git-mirror · Nov 1, 2010 · d199fbe · d199fbe
1 parent 295f718
commit d199fbe
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diff --git a/[refs] b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: edc9a958fd31ef1d89f9eaee82b2a3882c8e34c9
+refs/heads/master: 5aefa34fada9d17a00635516688de34702451708
diff --git a/trunk/Documentation/filesystems/Locking b/trunk/Documentation/filesystems/Locking
@@ -322,13 +322,15 @@ fl_release_private:	yes	yes
 prototypes:
 	int (*fl_compare_owner)(struct file_lock *, struct file_lock *);
 	void (*fl_notify)(struct file_lock *);  /* unblock callback */
+	void (*fl_copy_lock)(struct file_lock *, struct file_lock *);
 	void (*fl_release_private)(struct file_lock *);
 	void (*fl_break)(struct file_lock *); /* break_lease callback */
 
 locking rules:
 			BKL	may block
 fl_compare_owner:	yes	no
 fl_notify:		yes	no
+fl_copy_lock:		yes	no
 fl_release_private:	yes	yes
 fl_break:		yes	no
 

diff --git a/trunk/Documentation/i2c/busses/i2c-i801 b/trunk/Documentation/i2c/busses/i2c-i801
@@ -15,14 +15,10 @@ Supported adapters:
   * Intel 82801I (ICH9)
   * Intel EP80579 (Tolapai)
   * Intel 82801JI (ICH10)
-  * Intel 5/3400 Series (PCH)
+  * Intel 3400/5 Series (PCH)
   * Intel Cougar Point (PCH)
-  * Intel Patsburg (PCH)
    Datasheets: Publicly available at the Intel website
 
-On Intel Patsburg and later chipsets, both the normal host SMBus controller
-and the additional 'Integrated Device Function' controllers are supported.
-
 Authors: 
 	Mark Studebaker <mdsxyz123@yahoo.com>
 	Jean Delvare <khali@linux-fr.org>

diff --git a/trunk/Documentation/scsi/ChangeLog.megaraid_sas b/trunk/Documentation/scsi/ChangeLog.megaraid_sas
@@ -1,50 +1,3 @@
-1 Release Date    : Thur.  May 03, 2010 09:12:45 PST 2009 -
-			(emaild-id:megaraidlinux@lsi.com)
-			Bo Yang
-
-2 Current Version : 00.00.04.31-rc1
-3 Older Version   : 00.00.04.17.1-rc1
-
-1.	Add the Online Controller Reset (OCR) to the Driver.
-	OCR is the new feature for megaraid_sas driver which
-	will allow the fw to do the chip reset which will not
-	affact the OS behavious.
-
-	To add the OCR support, driver need to do:
-		a). reset the controller chips -- Xscale and Gen2 which
-		will change the function calls and add the reset function
-		related to this two chips.
-
-		b). during the reset, driver will store the pending cmds
-		which not returned by FW to driver's pending queue.  Driver
-		will re-issue those pending cmds again to FW after the OCR
-		finished.
-
-		c). In driver's timeout routine, driver will report to
-		OS as reset. Also driver's queue routine will block the
-		cmds until the OCR finished.
-
-		d). in Driver's ISR routine, if driver get the FW state as
-		state change, FW in Failure status and FW support online controller
-		reset (OCR), driver will start to do the controller reset.
-
-		e). In driver's IOCTL routine, the application cmds will wait for the
-		OCR to finish, then issue the cmds to FW.
-
-		f). Before driver kill adapter, driver will do last chance of
-		OCR to see if driver can bring back the FW.
-
-2.	Add the support update flag to the driver to tell LSI megaraid_sas
-	application which driver will support the device update.  So application
-	will not need to do the device update after application add/del the device
-	from the system.
-3.	In driver's timeout routine, driver will do three time reset if fw is in
-	failed state.  Driver will kill adapter if can't bring back FW after the
-	this three times reset.
-4.	Add the input parameter max_sectors to 1MB support to our GEN2 controller.
-	customer can use the input paramenter max_sectors to add 1MB support to GEN2
-	controller.
-
 1 Release Date    : Thur.  Oct 29, 2009 09:12:45 PST 2009 -
 			(emaild-id:megaraidlinux@lsi.com)
 			Bo Yang

diff --git a/trunk/MAINTAINERS b/trunk/MAINTAINERS
@@ -1757,7 +1757,6 @@ L:	linux-cris-kernel@axis.com
 W:	http://developer.axis.com
 S:	Maintained
 F:	arch/cris/
-F:	drivers/serial/crisv10.*
 
 CRYPTO API
 M:	Herbert Xu <herbert@gondor.apana.org.au>

diff --git a/trunk/Makefile b/trunk/Makefile
@@ -1,7 +1,7 @@
 VERSION = 2
 PATCHLEVEL = 6
-SUBLEVEL = 37
-EXTRAVERSION = -rc1
+SUBLEVEL = 36
+EXTRAVERSION =
 NAME = Flesh-Eating Bats with Fangs
 
 # *DOCUMENTATION*

diff --git a/trunk/arch/arm/mach-u300/spi.c b/trunk/arch/arm/mach-u300/spi.c
@@ -67,7 +67,7 @@ static struct spi_board_info u300_spi_devices[] = {
 		.bus_num        = 0, /* Only one bus on this chip */
 		.chip_select    = 0,
 		/* Means SPI_CS_HIGH, change if e.g low CS */
-		.mode           = SPI_MODE_1 | SPI_LOOP,
+		.mode           = SPI_MODE_1 | SPI_LSB_FIRST | SPI_LOOP,
 	},
 #endif
 };

diff --git a/trunk/arch/sh/Kconfig b/trunk/arch/sh/Kconfig
@@ -193,7 +193,6 @@ config CPU_SH2
 config CPU_SH2A
 	bool
 	select CPU_SH2
-	select UNCACHED_MAPPING
 
 config CPU_SH3
 	bool

diff --git a/trunk/arch/sh/boards/mach-se/7206/irq.c b/trunk/arch/sh/boards/mach-se/7206/irq.c
@@ -139,13 +139,11 @@ void __init init_se7206_IRQ(void)
 	make_se7206_irq(IRQ0_IRQ); /* SMC91C111 */
 	make_se7206_irq(IRQ1_IRQ); /* ATA */
 	make_se7206_irq(IRQ3_IRQ); /* SLOT / PCM */
-
-	__raw_writew(__raw_readw(INTC_ICR1) | 0x000b, INTC_ICR); /* ICR1 */
+	__raw_writew(inw(INTC_ICR1) | 0x000b ,INTC_ICR1 ) ; /* ICR1 */
 
 	/* FPGA System register setup*/
 	__raw_writew(0x0000,INTSTS0); /* Clear INTSTS0 */
 	__raw_writew(0x0000,INTSTS1); /* Clear INTSTS1 */
-
 	/* IRQ0=LAN, IRQ1=ATA, IRQ3=SLT,PCM */
 	__raw_writew(0x0001,INTSEL);
 }
diff --git a/trunk/arch/sh/include/asm/addrspace.h b/trunk/arch/sh/include/asm/addrspace.h
@@ -44,10 +44,10 @@
 /*
  * These will never work in 32-bit, don't even bother.
  */
-#define P1SEGADDR(a)	({ (void)(a); BUG(); NULL; })
-#define P2SEGADDR(a)	({ (void)(a); BUG(); NULL; })
-#define P3SEGADDR(a)	({ (void)(a); BUG(); NULL; })
-#define P4SEGADDR(a)	({ (void)(a); BUG(); NULL; })
+#define P1SEGADDR(a)	__futile_remapping_attempt
+#define P2SEGADDR(a)	__futile_remapping_attempt
+#define P3SEGADDR(a)	__futile_remapping_attempt
+#define P4SEGADDR(a)	__futile_remapping_attempt
 #endif
 #endif /* P1SEG */
 

diff --git a/trunk/arch/sh/include/asm/system.h b/trunk/arch/sh/include/asm/system.h
@@ -10,7 +10,6 @@
 #include <linux/compiler.h>
 #include <linux/linkage.h>
 #include <asm/types.h>
-#include <asm/uncached.h>
 
 #define AT_VECTOR_SIZE_ARCH 5 /* entries in ARCH_DLINFO */
 
@@ -138,6 +137,9 @@ extern unsigned int instruction_size(unsigned int insn);
 #define instruction_size(insn)	(4)
 #endif
 
+extern unsigned long cached_to_uncached;
+extern unsigned long uncached_size;
+
 void per_cpu_trap_init(void);
 void default_idle(void);
 void cpu_idle_wait(void);

diff --git a/trunk/arch/sh/include/asm/system_32.h b/trunk/arch/sh/include/asm/system_32.h
@@ -145,6 +145,42 @@ do {								\
 		__restore_dsp(prev);				\
 } while (0)
 
+/*
+ * Jump to uncached area.
+ * When handling TLB or caches, we need to do it from an uncached area.
+ */
+#define jump_to_uncached()			\
+do {						\
+	unsigned long __dummy;			\
+						\
+	__asm__ __volatile__(			\
+		"mova	1f, %0\n\t"		\
+		"add	%1, %0\n\t"		\
+		"jmp	@%0\n\t"		\
+		" nop\n\t"			\
+		".balign 4\n"			\
+		"1:"				\
+		: "=&z" (__dummy)		\
+		: "r" (cached_to_uncached));	\
+} while (0)
+
+/*
+ * Back to cached area.
+ */
+#define back_to_cached()				\
+do {							\
+	unsigned long __dummy;				\
+	ctrl_barrier();					\
+	__asm__ __volatile__(				\
+		"mov.l	1f, %0\n\t"			\
+		"jmp	@%0\n\t"			\
+		" nop\n\t"				\
+		".balign 4\n"				\
+		"1:	.long 2f\n"			\
+		"2:"					\
+		: "=&r" (__dummy));			\
+} while (0)
+
 #ifdef CONFIG_CPU_HAS_SR_RB
 #define lookup_exception_vector()	\
 ({					\

diff --git a/trunk/arch/sh/include/asm/system_64.h b/trunk/arch/sh/include/asm/system_64.h
@@ -34,6 +34,9 @@ do {								\
 			      &next->thread);			\
 } while (0)
 
+#define jump_to_uncached()	do { } while (0)
+#define back_to_cached()	do { } while (0)
+
 #define __icbi(addr)	__asm__ __volatile__ ( "icbi %0, 0\n\t" : : "r" (addr))
 #define __ocbp(addr)	__asm__ __volatile__ ( "ocbp %0, 0\n\t" : : "r" (addr))
 #define __ocbi(addr)	__asm__ __volatile__ ( "ocbi %0, 0\n\t" : : "r" (addr))

diff --git a/trunk/arch/sh/include/asm/uncached.h b/trunk/arch/sh/include/asm/uncached.h
@@ -4,55 +4,15 @@
 #include <linux/bug.h>
 
 #ifdef CONFIG_UNCACHED_MAPPING
-extern unsigned long cached_to_uncached;
-extern unsigned long uncached_size;
 extern unsigned long uncached_start, uncached_end;
 
 extern int virt_addr_uncached(unsigned long kaddr);
 extern void uncached_init(void);
 extern void uncached_resize(unsigned long size);
-
-/*
- * Jump to uncached area.
- * When handling TLB or caches, we need to do it from an uncached area.
- */
-#define jump_to_uncached()			\
-do {						\
-	unsigned long __dummy;			\
-						\
-	__asm__ __volatile__(			\
-		"mova	1f, %0\n\t"		\
-		"add	%1, %0\n\t"		\
-		"jmp	@%0\n\t"		\
-		" nop\n\t"			\
-		".balign 4\n"			\
-		"1:"				\
-		: "=&z" (__dummy)		\
-		: "r" (cached_to_uncached));	\
-} while (0)
-
-/*
- * Back to cached area.
- */
-#define back_to_cached()				\
-do {							\
-	unsigned long __dummy;				\
-	ctrl_barrier();					\
-	__asm__ __volatile__(				\
-		"mov.l	1f, %0\n\t"			\
-		"jmp	@%0\n\t"			\
-		" nop\n\t"				\
-		".balign 4\n"				\
-		"1:	.long 2f\n"			\
-		"2:"					\
-		: "=&r" (__dummy));			\
-} while (0)
 #else
 #define virt_addr_uncached(kaddr)	(0)
 #define uncached_init()			do { } while (0)
 #define uncached_resize(size)		BUG()
-#define jump_to_uncached()		do { } while (0)
-#define back_to_cached()		do { } while (0)
 #endif
 
 #endif /* __ASM_SH_UNCACHED_H */
diff --git a/trunk/arch/sh/mm/Kconfig b/trunk/arch/sh/mm/Kconfig
@@ -79,7 +79,7 @@ config 29BIT
 
 config 32BIT
 	bool
-	default y if CPU_SH5 || !MMU
+	default y if CPU_SH5
 
 config PMB
 	bool "Support 32-bit physical addressing through PMB"

diff --git a/trunk/arch/sh/mm/consistent.c b/trunk/arch/sh/mm/consistent.c
@@ -79,20 +79,21 @@ void dma_generic_free_coherent(struct device *dev, size_t size,
 void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
 		    enum dma_data_direction direction)
 {
-	void *addr;
-
-	addr = __in_29bit_mode() ?
-	       (void *)P1SEGADDR((unsigned long)vaddr) : vaddr;
+#if defined(CONFIG_CPU_SH5) || defined(CONFIG_PMB)
+	void *p1addr = vaddr;
+#else
+	void *p1addr = (void*) P1SEGADDR((unsigned long)vaddr);
+#endif
 
 	switch (direction) {
 	case DMA_FROM_DEVICE:		/* invalidate only */
-		__flush_invalidate_region(addr, size);
+		__flush_invalidate_region(p1addr, size);
 		break;
 	case DMA_TO_DEVICE:		/* writeback only */
-		__flush_wback_region(addr, size);
+		__flush_wback_region(p1addr, size);
 		break;
 	case DMA_BIDIRECTIONAL:		/* writeback and invalidate */
-		__flush_purge_region(addr, size);
+		__flush_purge_region(p1addr, size);
 		break;
 	default:
 		BUG();

diff --git a/trunk/arch/sh/mm/uncached.c b/trunk/arch/sh/mm/uncached.c
@@ -28,7 +28,7 @@ EXPORT_SYMBOL(virt_addr_uncached);
 
 void __init uncached_init(void)
 {
-#if defined(CONFIG_29BIT) || !defined(CONFIG_MMU)
+#ifdef CONFIG_29BIT
 	uncached_start = P2SEG;
 #else
 	uncached_start = memory_end;

diff --git a/trunk/drivers/i2c/busses/Kconfig b/trunk/drivers/i2c/busses/Kconfig
@@ -99,7 +99,6 @@ config I2C_I801
 	    ICH10
 	    5/3400 Series (PCH)
 	    Cougar Point (PCH)
-	    Patsburg (PCH)
 
 	  This driver can also be built as a module.  If so, the module
 	  will be called i2c-i801.