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gxfb: clean up register definitions
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This does the following in preparation for register saving:
  - moves the register definitions from video_gx.h and display_gx.h into
    gxfb.h.
  - renames GX_* registers to match their section (ie, VP_).
  - renames register bitfields to match the data sheet (ie,
    DC_DCFG_TGEN -> DC_DISPLAY_CFG_TGEN).
  - for DC registers, rather than defining to specific addresses, use
    an enum to number them sequentially and just multiply by 4(bytes) to
    access them (in read_dc/write_dc).
  - for VP and FP registers, use an enum and multiple by 8 (bytes).  They're
    64bit registers.

Signed-off-by: Andres Salomon <dilinger@debian.org>
Cc: Jordan Crouse <jordan.crouse@amd.com>
Cc: "Antonino A. Daplas" <adaplas@pol.net>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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Andres Salomon authored and Linus Torvalds committed Apr 28, 2008
1 parent ab06aaf commit d255114
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Showing 5 changed files with 276 additions and 183 deletions.
28 changes: 15 additions & 13 deletions drivers/video/geode/display_gx.c
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Original file line number Diff line number Diff line change
Expand Up @@ -51,20 +51,21 @@ static void gx_set_mode(struct fb_info *info)
int vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal;

/* Unlock the display controller registers. */
write_dc(par, DC_UNLOCK, DC_UNLOCK_CODE);
write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);

gcfg = read_dc(par, DC_GENERAL_CFG);
dcfg = read_dc(par, DC_DISPLAY_CFG);

/* Disable the timing generator. */
dcfg &= ~(DC_DCFG_TGEN);
dcfg &= ~DC_DISPLAY_CFG_TGEN;
write_dc(par, DC_DISPLAY_CFG, dcfg);

/* Wait for pending memory requests before disabling the FIFO load. */
udelay(100);

/* Disable FIFO load and compression. */
gcfg &= ~(DC_GCFG_DFLE | DC_GCFG_CMPE | DC_GCFG_DECE);
gcfg &= ~(DC_GENERAL_CFG_DFLE | DC_GENERAL_CFG_CMPE |
DC_GENERAL_CFG_DECE);
write_dc(par, DC_GENERAL_CFG, gcfg);

/* Setup DCLK and its divisor. */
Expand All @@ -75,12 +76,13 @@ static void gx_set_mode(struct fb_info *info)
*/

/* Clear all unused feature bits. */
gcfg &= DC_GCFG_YUVM | DC_GCFG_VDSE;
gcfg &= DC_GENERAL_CFG_YUVM | DC_GENERAL_CFG_VDSE;
dcfg = 0;

/* Set FIFO priority (default 6/5) and enable. */
/* FIXME: increase fifo priority for 1280x1024 and higher modes? */
gcfg |= (6 << DC_GCFG_DFHPEL_POS) | (5 << DC_GCFG_DFHPSL_POS) | DC_GCFG_DFLE;
gcfg |= (6 << DC_GENERAL_CFG_DFHPEL_SHIFT) |
(5 << DC_GENERAL_CFG_DFHPSL_SHIFT) | DC_GENERAL_CFG_DFLE;

/* Framebuffer start offset. */
write_dc(par, DC_FB_ST_OFFSET, 0);
Expand All @@ -92,25 +94,25 @@ static void gx_set_mode(struct fb_info *info)


/* Enable graphics and video data and unmask address lines. */
dcfg |= DC_DCFG_GDEN | DC_DCFG_VDEN | DC_DCFG_A20M | DC_DCFG_A18M;
dcfg |= DC_DISPLAY_CFG_GDEN | DC_DISPLAY_CFG_VDEN |
DC_DISPLAY_CFG_A20M | DC_DISPLAY_CFG_A18M;

/* Set pixel format. */
switch (info->var.bits_per_pixel) {
case 8:
dcfg |= DC_DCFG_DISP_MODE_8BPP;
dcfg |= DC_DISPLAY_CFG_DISP_MODE_8BPP;
break;
case 16:
dcfg |= DC_DCFG_DISP_MODE_16BPP;
dcfg |= DC_DCFG_16BPP_MODE_565;
dcfg |= DC_DISPLAY_CFG_DISP_MODE_16BPP;
break;
case 32:
dcfg |= DC_DCFG_DISP_MODE_24BPP;
dcfg |= DC_DCFG_PALB;
dcfg |= DC_DISPLAY_CFG_DISP_MODE_24BPP;
dcfg |= DC_DISPLAY_CFG_PALB;
break;
}

/* Enable timing generator. */
dcfg |= DC_DCFG_TGEN;
dcfg |= DC_DISPLAY_CFG_TGEN;

/* Horizontal and vertical timings. */
hactive = info->var.xres;
Expand Down Expand Up @@ -148,7 +150,7 @@ static void gx_set_mode(struct fb_info *info)
par->vid_ops->configure_display(info);

/* Relock display controller registers */
write_dc(par, DC_UNLOCK, 0);
write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK);
}

static void gx_set_hw_palette_reg(struct fb_info *info, unsigned regno,
Expand Down
78 changes: 0 additions & 78 deletions drivers/video/geode/display_gx.h
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Original file line number Diff line number Diff line change
Expand Up @@ -19,82 +19,4 @@ extern struct geode_dc_ops gx_dc_ops;
/* MSR that tells us if a TFT or CRT is attached */
#define GLD_MSR_CONFIG_DM_FP 0x40

/* Display controller registers */

#define DC_UNLOCK 0x00
# define DC_UNLOCK_CODE 0x00004758

#define DC_GENERAL_CFG 0x04
# define DC_GCFG_DFLE 0x00000001
# define DC_GCFG_CURE 0x00000002
# define DC_GCFG_ICNE 0x00000004
# define DC_GCFG_VIDE 0x00000008
# define DC_GCFG_CMPE 0x00000020
# define DC_GCFG_DECE 0x00000040
# define DC_GCFG_VGAE 0x00000080
# define DC_GCFG_DFHPSL_MASK 0x00000F00
# define DC_GCFG_DFHPSL_POS 8
# define DC_GCFG_DFHPEL_MASK 0x0000F000
# define DC_GCFG_DFHPEL_POS 12
# define DC_GCFG_STFM 0x00010000
# define DC_GCFG_FDTY 0x00020000
# define DC_GCFG_VGAFT 0x00040000
# define DC_GCFG_VDSE 0x00080000
# define DC_GCFG_YUVM 0x00100000
# define DC_GCFG_VFSL 0x00800000
# define DC_GCFG_SIGE 0x01000000
# define DC_GCFG_SGRE 0x02000000
# define DC_GCFG_SGFR 0x04000000
# define DC_GCFG_CRC_MODE 0x08000000
# define DC_GCFG_DIAG 0x10000000
# define DC_GCFG_CFRW 0x20000000

#define DC_DISPLAY_CFG 0x08
# define DC_DCFG_TGEN 0x00000001
# define DC_DCFG_GDEN 0x00000008
# define DC_DCFG_VDEN 0x00000010
# define DC_DCFG_TRUP 0x00000040
# define DC_DCFG_DISP_MODE_MASK 0x00000300
# define DC_DCFG_DISP_MODE_8BPP 0x00000000
# define DC_DCFG_DISP_MODE_16BPP 0x00000100
# define DC_DCFG_DISP_MODE_24BPP 0x00000200
# define DC_DCFG_16BPP_MODE_MASK 0x00000c00
# define DC_DCFG_16BPP_MODE_565 0x00000000
# define DC_DCFG_16BPP_MODE_555 0x00000100
# define DC_DCFG_16BPP_MODE_444 0x00000200
# define DC_DCFG_DCEN 0x00080000
# define DC_DCFG_PALB 0x02000000
# define DC_DCFG_FRLK 0x04000000
# define DC_DCFG_VISL 0x08000000
# define DC_DCFG_FRSL 0x20000000
# define DC_DCFG_A18M 0x40000000
# define DC_DCFG_A20M 0x80000000

#define DC_FB_ST_OFFSET 0x10

#define DC_LINE_SIZE 0x30
# define DC_LINE_SIZE_FB_LINE_SIZE_MASK 0x000007ff
# define DC_LINE_SIZE_FB_LINE_SIZE_POS 0
# define DC_LINE_SIZE_CB_LINE_SIZE_MASK 0x007f0000
# define DC_LINE_SIZE_CB_LINE_SIZE_POS 16
# define DC_LINE_SIZE_VID_LINE_SIZE_MASK 0xff000000
# define DC_LINE_SIZE_VID_LINE_SIZE_POS 24

#define DC_GFX_PITCH 0x34
# define DC_GFX_PITCH_FB_PITCH_MASK 0x0000ffff
# define DC_GFX_PITCH_FB_PITCH_POS 0
# define DC_GFX_PITCH_CB_PITCH_MASK 0xffff0000
# define DC_GFX_PITCH_CB_PITCH_POS 16

#define DC_H_ACTIVE_TIMING 0x40
#define DC_H_BLANK_TIMING 0x44
#define DC_H_SYNC_TIMING 0x48
#define DC_V_ACTIVE_TIMING 0x50
#define DC_V_BLANK_TIMING 0x54
#define DC_V_SYNC_TIMING 0x58

#define DC_PAL_ADDRESS 0x70
#define DC_PAL_DATA 0x74

#define DC_GLIU0_MEM_OFFSET 0x84
#endif /* !__DISPLAY_GX1_H__ */
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