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powerpc/85xx: Rename p2040_rdb.c to p2041_rdb.c
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There's only p2041rdb board for official release, but the p2041 silicon
on the board can be converted to p2040 silicon without XAUI and L2 cache
function, then the board becomes p2040rdb board. so we use the file name
p2041_rdb.c to handle P2040RDB board and P2041RDB board which is also
consistent with the board name under U-Boot.

During the rename we make few other minor changes to the device tree:
* Move USB phy setting into p2041si.dtsi as its SoC not board defined
* Convert PCI clock-frequency to decimal to be more readable

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Mingkai Hu authored and Kumar Gala committed Oct 7, 2011
1 parent d70cb31 commit d313376
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Showing 6 changed files with 50 additions and 55 deletions.
13 changes: 4 additions & 9 deletions arch/powerpc/boot/dts/p2040rdb.dts → arch/powerpc/boot/dts/p2041rdb.dts
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/*
* P2040RDB Device Tree Source
* P2041RDB Device Tree Source
*
* Copyright 2011 Freescale Semiconductor Inc.
*
Expand Down Expand Up @@ -32,11 +32,11 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/

/include/ "p2040si.dtsi"
/include/ "p2041si.dtsi"

/ {
model = "fsl,P2040RDB";
compatible = "fsl,P2040RDB";
model = "fsl,P2041RDB";
compatible = "fsl,P2041RDB";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&mpic>;
Expand Down Expand Up @@ -97,13 +97,8 @@
};
};

usb0: usb@210000 {
phy_type = "utmi";
};

usb1: usb@211000 {
dr_mode = "host";
phy_type = "utmi";
};
};

Expand Down
64 changes: 32 additions & 32 deletions arch/powerpc/boot/dts/p2040si.dtsi → arch/powerpc/boot/dts/p2041si.dtsi
View file
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/*
* P2040 Silicon Device Tree Source
* P2041 Silicon Device Tree Source
*
* Copyright 2011 Freescale Semiconductor Inc.
*
Expand Down Expand Up @@ -35,7 +35,7 @@
/dts-v1/;

/ {
compatible = "fsl,P2040";
compatible = "fsl,P2041";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&mpic>;
Expand Down Expand Up @@ -135,7 +135,7 @@
};

cpc: l3-cache-controller@10000 {
compatible = "fsl,p2040-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
compatible = "fsl,p2041-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
reg = <0x10000 0x1000>;
interrupts = <16 2 1 27>;
};
Expand Down Expand Up @@ -226,7 +226,7 @@
};

clockgen: global-utilities@e1000 {
compatible = "fsl,p2040-clockgen", "fsl,qoriq-clockgen-1.0";
compatible = "fsl,p2041-clockgen", "fsl,qoriq-clockgen-1.0";
reg = <0xe1000 0x1000>;
clock-frequency = <0>;
};
Expand All @@ -238,45 +238,45 @@
};

sfp: sfp@e8000 {
compatible = "fsl,p2040-sfp", "fsl,qoriq-sfp-1.0";
compatible = "fsl,p2041-sfp", "fsl,qoriq-sfp-1.0";
reg = <0xe8000 0x1000>;
};

serdes: serdes@ea000 {
compatible = "fsl,p2040-serdes";
compatible = "fsl,p2041-serdes";
reg = <0xea000 0x1000>;
};

dma0: dma@100300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,p2040-dma", "fsl,eloplus-dma";
compatible = "fsl,p2041-dma", "fsl,eloplus-dma";
reg = <0x100300 0x4>;
ranges = <0x0 0x100100 0x200>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,p2040-dma-channel",
compatible = "fsl,p2041-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
interrupts = <28 2 0 0>;
};
dma-channel@80 {
compatible = "fsl,p2040-dma-channel",
compatible = "fsl,p2041-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupts = <29 2 0 0>;
};
dma-channel@100 {
compatible = "fsl,p2040-dma-channel",
compatible = "fsl,p2041-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupts = <30 2 0 0>;
};
dma-channel@180 {
compatible = "fsl,p2040-dma-channel",
compatible = "fsl,p2041-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
Expand All @@ -287,33 +287,33 @@
dma1: dma@101300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,p2040-dma", "fsl,eloplus-dma";
compatible = "fsl,p2041-dma", "fsl,eloplus-dma";
reg = <0x101300 0x4>;
ranges = <0x0 0x101100 0x200>;
cell-index = <1>;
dma-channel@0 {
compatible = "fsl,p2040-dma-channel",
compatible = "fsl,p2041-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
cell-index = <0>;
interrupts = <32 2 0 0>;
};
dma-channel@80 {
compatible = "fsl,p2040-dma-channel",
compatible = "fsl,p2041-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupts = <33 2 0 0>;
};
dma-channel@100 {
compatible = "fsl,p2040-dma-channel",
compatible = "fsl,p2041-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupts = <34 2 0 0>;
};
dma-channel@180 {
compatible = "fsl,p2040-dma-channel",
compatible = "fsl,p2041-dma-channel",
"fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
Expand All @@ -324,22 +324,20 @@
spi@110000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,p2040-espi", "fsl,mpc8536-espi";
compatible = "fsl,p2041-espi", "fsl,mpc8536-espi";
reg = <0x110000 0x1000>;
interrupts = <53 0x2 0 0>;
fsl,espi-num-chipselects = <4>;

};

sdhc: sdhc@114000 {
compatible = "fsl,p2040-esdhc", "fsl,esdhc";
compatible = "fsl,p2041-esdhc", "fsl,esdhc";
reg = <0x114000 0x1000>;
interrupts = <48 2 0 0>;
sdhci,auto-cmd12;
clock-frequency = <0>;
};


i2c@118000 {
#address-cells = <1>;
#size-cells = <0>;
Expand Down Expand Up @@ -417,40 +415,42 @@
};

gpio0: gpio@130000 {
compatible = "fsl,p2040-gpio", "fsl,qoriq-gpio";
compatible = "fsl,p2041-gpio", "fsl,qoriq-gpio";
reg = <0x130000 0x1000>;
interrupts = <55 2 0 0>;
#gpio-cells = <2>;
gpio-controller;
};

usb0: usb@210000 {
compatible = "fsl,p2040-usb2-mph",
compatible = "fsl,p2041-usb2-mph",
"fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
reg = <0x210000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <44 0x2 0 0>;
phy_type = "utmi";
port0;
};

usb1: usb@211000 {
compatible = "fsl,p2040-usb2-dr",
compatible = "fsl,p2041-usb2-dr",
"fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
reg = <0x211000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <45 0x2 0 0>;
phy_type = "utmi";
};

sata@220000 {
compatible = "fsl,p2040-sata", "fsl,pq-sata-v2";
compatible = "fsl,p2041-sata", "fsl,pq-sata-v2";
reg = <0x220000 0x1000>;
interrupts = <68 0x2 0 0>;
};

sata@221000 {
compatible = "fsl,p2040-sata", "fsl,pq-sata-v2";
compatible = "fsl,p2041-sata", "fsl,pq-sata-v2";
reg = <0x221000 0x1000>;
interrupts = <69 0x2 0 0>;
};
Expand Down Expand Up @@ -534,19 +534,19 @@
};

localbus@ffe124000 {
compatible = "fsl,p2040-elbc", "fsl,elbc", "simple-bus";
compatible = "fsl,p2041-elbc", "fsl,elbc", "simple-bus";
interrupts = <25 2 0 0>;
#address-cells = <2>;
#size-cells = <1>;
};

pci0: pcie@ffe200000 {
compatible = "fsl,p2040-pcie", "fsl,qoriq-pcie-v2.2";
compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
device_type = "pci";
#size-cells = <2>;
#address-cells = <3>;
bus-range = <0x0 0xff>;
clock-frequency = <0x1fca055>;
clock-frequency = <33333333>;
fsl,msi = <&msi0>;
interrupts = <16 2 1 15>;
pcie@0 {
Expand All @@ -568,12 +568,12 @@
};

pci1: pcie@ffe201000 {
compatible = "fsl,p2040-pcie", "fsl,qoriq-pcie-v2.2";
compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
device_type = "pci";
#size-cells = <2>;
#address-cells = <3>;
bus-range = <0 0xff>;
clock-frequency = <0x1fca055>;
clock-frequency = <33333333>;
fsl,msi = <&msi1>;
interrupts = <16 2 1 14>;
pcie@0 {
Expand All @@ -595,12 +595,12 @@
};

pci2: pcie@ffe202000 {
compatible = "fsl,p2040-pcie", "fsl,qoriq-pcie-v2.2";
compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
device_type = "pci";
#size-cells = <2>;
#address-cells = <3>;
bus-range = <0x0 0xff>;
clock-frequency = <0x1fca055>;
clock-frequency = <33333333>;
fsl,msi = <&msi2>;
interrupts = <16 2 1 13>;
pcie@0 {
Expand Down
2 changes: 1 addition & 1 deletion arch/powerpc/configs/corenet32_smp_defconfig
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Original file line number Diff line number Diff line change
Expand Up @@ -23,7 +23,7 @@ CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_MODVERSIONS=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_P2040_RDB=y
CONFIG_P2041_RDB=y
CONFIG_P3041_DS=y
CONFIG_P4080_DS=y
CONFIG_P5020_DS=y
Expand Down
6 changes: 3 additions & 3 deletions arch/powerpc/platforms/85xx/Kconfig
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Original file line number Diff line number Diff line change
Expand Up @@ -171,8 +171,8 @@ config SBC8560
help
This option enables support for the Wind River SBC8560 board

config P2040_RDB
bool "Freescale P2040 RDB"
config P2041_RDB
bool "Freescale P2041 RDB"
select DEFAULT_UIMAGE
select PPC_E500MC
select PHYS_64BIT
Expand All @@ -182,7 +182,7 @@ config P2040_RDB
select HAS_RAPIDIO
select PPC_EPAPR_HV_PIC
help
This option enables support for the P2040 RDB board
This option enables support for the P2041 RDB board

config P3041_DS
bool "Freescale P3041 DS"
Expand Down
2 changes: 1 addition & 1 deletion arch/powerpc/platforms/85xx/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@ obj-$(CONFIG_MPC85xx_RDB) += mpc85xx_rdb.o
obj-$(CONFIG_P1010_RDB) += p1010rdb.o
obj-$(CONFIG_P1022_DS) += p1022_ds.o
obj-$(CONFIG_P1023_RDS) += p1023_rds.o
obj-$(CONFIG_P2040_RDB) += p2040_rdb.o corenet_ds.o
obj-$(CONFIG_P2041_RDB) += p2041_rdb.o corenet_ds.o
obj-$(CONFIG_P3041_DS) += p3041_ds.o corenet_ds.o
obj-$(CONFIG_P4080_DS) += p4080_ds.o corenet_ds.o
obj-$(CONFIG_P5020_DS) += p5020_ds.o corenet_ds.o
Expand Down
18 changes: 9 additions & 9 deletions arch/powerpc/platforms/85xx/p2040_rdb.c → arch/powerpc/platforms/85xx/p2041_rdb.c
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/*
* P2040 RDB Setup
* P2041 RDB Setup
*
* Copyright 2011 Freescale Semiconductor Inc.
*
Expand Down Expand Up @@ -35,18 +35,18 @@
/*
* Called very early, device-tree isn't unflattened
*/
static int __init p2040_rdb_probe(void)
static int __init p2041_rdb_probe(void)
{
unsigned long root = of_get_flat_dt_root();
#ifdef CONFIG_SMP
extern struct smp_ops_t smp_85xx_ops;
#endif

if (of_flat_dt_is_compatible(root, "fsl,P2040RDB"))
if (of_flat_dt_is_compatible(root, "fsl,P2041RDB"))
return 1;

/* Check if we're running under the Freescale hypervisor */
if (of_flat_dt_is_compatible(root, "fsl,P2040RDB-hv")) {
if (of_flat_dt_is_compatible(root, "fsl,P2041RDB-hv")) {
ppc_md.init_IRQ = ehv_pic_init;
ppc_md.get_irq = ehv_pic_get_irq;
ppc_md.restart = fsl_hv_restart;
Expand All @@ -66,9 +66,9 @@ static int __init p2040_rdb_probe(void)
return 0;
}

define_machine(p2040_rdb) {
.name = "P2040 RDB",
.probe = p2040_rdb_probe,
define_machine(p2041_rdb) {
.name = "P2041 RDB",
.probe = p2041_rdb_probe,
.setup_arch = corenet_ds_setup_arch,
.init_IRQ = corenet_ds_pic_init,
#ifdef CONFIG_PCI
Expand All @@ -81,8 +81,8 @@ define_machine(p2040_rdb) {
.power_save = e500_idle,
};

machine_device_initcall(p2040_rdb, corenet_ds_publish_devices);
machine_device_initcall(p2041_rdb, corenet_ds_publish_devices);

#ifdef CONFIG_SWIOTLB
machine_arch_initcall(p2040_rdb, swiotlb_setup_bus_notifier);
machine_arch_initcall(p2041_rdb, swiotlb_setup_bus_notifier);
#endif

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