Merge git://oak/home/sfr/kernels/iseries/work

arch/powerpc/kernel/Makefile

@@ -13,7 +13,7 @@ endif
 obj-y				:= semaphore.o cputable.o ptrace.o syscalls.o \
 				   signal_32.o pmc.o
 obj-$(CONFIG_PPC64)		+= setup_64.o binfmt_elf32.o sys_ppc32.o \
-				   ptrace32.o systbl.o
+				   signal_64.o ptrace32.o systbl.o
 obj-$(CONFIG_ALTIVEC)		+= vecemu.o vector.o
 obj-$(CONFIG_POWER4)		+= idle_power4.o
 obj-$(CONFIG_PPC_OF)		+= of_device.o

include/asm-ppc64/ppc32.h → arch/powerpc/kernel/ppc32.h

@@ -91,6 +91,22 @@ typedef struct sigaltstack_32 {
 	compat_size_t ss_size;
 } stack_32_t;
 
+struct pt_regs32 {
+	unsigned int gpr[32];
+	unsigned int nip;
+	unsigned int msr;
+	unsigned int orig_gpr3;		/* Used for restarting system calls */
+	unsigned int ctr;
+	unsigned int link;
+	unsigned int xer;
+	unsigned int ccr;
+	unsigned int mq;		/* 601 only (not used at present) */
+	unsigned int trap;		/* Reason for being here */
+	unsigned int dar;		/* Fault registers */
+	unsigned int dsisr;
+	unsigned int result;		/* Result of a system call */
+};
+
 struct sigcontext32 {
 	unsigned int	_unused[4];
 	int		signal;

arch/powerpc/kernel/signal_32.c

@@ -43,7 +43,7 @@
 #include <asm/uaccess.h>
 #include <asm/cacheflush.h>
 #ifdef CONFIG_PPC64
-#include <asm/ppc32.h>
+#include "ppc32.h"
 #include <asm/ppcdebug.h>
 #include <asm/unistd.h>
 #include <asm/vdso.h>

arch/ppc64/kernel/Makefile

@@ -12,7 +12,6 @@ obj-y               :=	misc.o prom.o
 endif
 
 obj-y               +=	irq.o idle.o dma.o \
-			signal.o \
 			align.o pacaData.o \
 			udbg.o ioctl32.o \
 			rtc.o \

include/asm-ppc64/ptrace.h → include/asm-powerpc/ptrace.h

@@ -1,5 +1,5 @@
-#ifndef _PPC64_PTRACE_H
-#define _PPC64_PTRACE_H
+#ifndef _ASM_POWERPC_PTRACE_H
+#define _ASM_POWERPC_PTRACE_H
 
 /*
  * Copyright (C) 2001 PPC64 Team, IBM Corp
@@ -16,7 +16,7 @@
  * that the overall structure is a multiple of 16 bytes in length.
  *
  * Note that the offsets of the fields in this struct correspond with
- * the PT_* values below.  This simplifies arch/ppc64/kernel/ptrace.c.
+ * the PT_* values below.  This simplifies arch/powerpc/kernel/ptrace.c.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -30,70 +30,96 @@ struct pt_regs {
 	unsigned long gpr[32];
 	unsigned long nip;
 	unsigned long msr;
-	unsigned long orig_gpr3; /* Used for restarting system calls */
+	unsigned long orig_gpr3;	/* Used for restarting system calls */
 	unsigned long ctr;
 	unsigned long link;
 	unsigned long xer;
 	unsigned long ccr;
-	unsigned long softe;	/* Soft enabled/disabled */
-	unsigned long trap;	/* Reason for being here */
-	unsigned long dar;	/* Fault registers */
-	unsigned long dsisr;
-	unsigned long result;	/* Result of a system call */
+#ifdef __powerpc64__
+	unsigned long softe;		/* Soft enabled/disabled */
+#else
+	unsigned long mq;		/* 601 only (not used at present) */
+					/* Used on APUS to hold IPL value. */
+#endif
+	unsigned long trap;		/* Reason for being here */
+	/* N.B. for critical exceptions on 4xx, the dar and dsisr
+	   fields are overloaded to hold srr0 and srr1. */
+	unsigned long dar;		/* Fault registers */
+	unsigned long dsisr;		/* on 4xx/Book-E used for ESR */
+	unsigned long result;		/* Result of a system call */
 };
 
-struct pt_regs32 {
-	unsigned int gpr[32];
-	unsigned int nip;
-	unsigned int msr;
-	unsigned int orig_gpr3;	/* Used for restarting system calls */
-	unsigned int ctr;
-	unsigned int link;
-	unsigned int xer;
-	unsigned int ccr;
-	unsigned int mq;	/* 601 only (not used at present) */
-	unsigned int trap;	/* Reason for being here */
-	unsigned int dar;	/* Fault registers */
-	unsigned int dsisr;
-	unsigned int result;	/* Result of a system call */
-};
+#endif /* __ASSEMBLY__ */
 
 #ifdef __KERNEL__
 
-#define instruction_pointer(regs) ((regs)->nip)
+#ifdef __powerpc64__
+
+#define STACK_FRAME_OVERHEAD	112	/* size of minimum stack frame */
+
+/* Size of dummy stack frame allocated when calling signal handler. */
+#define __SIGNAL_FRAMESIZE	128
+#define __SIGNAL_FRAMESIZE32	64
+
+#else /* __powerpc64__ */
+
+#define STACK_FRAME_OVERHEAD	16	/* size of minimum stack frame */
+
+/* Size of stack frame allocated when calling signal handler. */
+#define __SIGNAL_FRAMESIZE	64
+
+#endif /* __powerpc64__ */
 
+#ifndef __ASSEMBLY__
+
+#define instruction_pointer(regs) ((regs)->nip)
 #ifdef CONFIG_SMP
 extern unsigned long profile_pc(struct pt_regs *regs);
 #else
 #define profile_pc(regs) instruction_pointer(regs)
 #endif
 
+#ifdef __powerpc64__
 #define user_mode(regs) ((((regs)->msr) >> MSR_PR_LG) & 0x1)
+#else
+#define user_mode(regs) (((regs)->msr & MSR_PR) != 0)
+#endif
 
 #define force_successful_syscall_return()   \
-		(current_thread_info()->syscall_noerror = 1)
+	do { \
+		current_thread_info()->syscall_noerror = 1; \
+	} while(0)
 
 /*
  * We use the least-significant bit of the trap field to indicate
  * whether we have saved the full set of registers, or only a
  * partial set.  A 1 there means the partial set.
+ * On 4xx we use the next bit to indicate whether the exception
+ * is a critical exception (1 means it is).
  */
 #define FULL_REGS(regs)		(((regs)->trap & 1) == 0)
+#ifndef __powerpc64__
+#define IS_CRITICAL_EXC(regs)	(((regs)->trap & 2) == 0)
+#endif /* ! __powerpc64__ */
 #define TRAP(regs)		((regs)->trap & ~0xF)
+#ifdef __powerpc64__
 #define CHECK_FULL_REGS(regs)	BUG_ON(regs->trap & 1)
-
-#endif /* __KERNEL__ */
+#else
+#define CHECK_FULL_REGS(regs)						      \
+do {									      \
+	if ((regs)->trap & 1)						      \
+		printk(KERN_CRIT "%s: partial register set\n", __FUNCTION__); \
+} while (0)
+#endif /* __powerpc64__ */
 
 #endif /* __ASSEMBLY__ */
 
-#define STACK_FRAME_OVERHEAD	112	/* size of minimum stack frame */
-
-/* Size of dummy stack frame allocated when calling signal handler. */
-#define __SIGNAL_FRAMESIZE	128
-#define __SIGNAL_FRAMESIZE32	64
+#endif /* __KERNEL__ */
 
 /*
  * Offsets used by 'ptrace' system call interface.
+ * These can't be changed without breaking binary compatibility
+ * with MkLinux, etc.
  */
 #define PT_R0	0
 #define PT_R1	1
@@ -137,18 +163,25 @@ extern unsigned long profile_pc(struct pt_regs *regs);
 #define PT_LNK	36
 #define PT_XER	37
 #define PT_CCR	38
+#ifndef __powerpc64__
+#define PT_MQ	39
+#else
 #define PT_SOFTE 39
 #define PT_TRAP	40
 #define PT_DAR	41
 #define PT_DSISR 42
 #define PT_RESULT 43
+#endif
 
-#define PT_FPR0	48
+#define PT_FPR0	48	/* each FP reg occupies 2 slots in this space */
+
+#ifndef __powerpc64__
+
+#define PT_FPR31 (PT_FPR0 + 2*31)
+#define PT_FPSCR (PT_FPR0 + 2*32 + 1)
+
+#else /* __powerpc64__ */
 
-/*
- * Kernel and userspace will both use this PT_FPSCR value.  32-bit apps will
- * have visibility to the asm-ppc/ptrace.h header instead of this one.
- */
 #define PT_FPSCR (PT_FPR0 + 32)	/* each FP reg occupies 1 slot in 64-bit space */
 
 #ifdef __KERNEL__
@@ -165,29 +198,29 @@ extern unsigned long profile_pc(struct pt_regs *regs);
 #define PT_VRSAVE_32 (PT_VR0 + 33*4)
 #endif
 
+#endif /* __powerpc64__ */
+
 /*
- * Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go. 
- * The transfer totals 34 quadword.  Quadwords 0-31 contain the 
- * corresponding vector registers.  Quadword 32 contains the vscr as the 
- * last word (offset 12) within that quadword.  Quadword 33 contains the 
+ * Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go.
+ * The transfer totals 34 quadword.  Quadwords 0-31 contain the
+ * corresponding vector registers.  Quadword 32 contains the vscr as the
+ * last word (offset 12) within that quadword.  Quadword 33 contains the
  * vrsave as the first word (offset 0) within the quadword.
  *
- * This definition of the VMX state is compatible with the current PPC32 
- * ptrace interface.  This allows signal handling and ptrace to use the same 
- * structures.  This also simplifies the implementation of a bi-arch 
+ * This definition of the VMX state is compatible with the current PPC32
+ * ptrace interface.  This allows signal handling and ptrace to use the same
+ * structures.  This also simplifies the implementation of a bi-arch
  * (combined (32- and 64-bit) gdb.
  */
 #define PTRACE_GETVRREGS	18
 #define PTRACE_SETVRREGS	19
 
-/*
- * While we dont have 64bit book E processors, we need to reserve the
- * relevant ptrace calls for 32bit compatibility.
- */
-#if 0
-#define PTRACE_GETEVRREGS       20
-#define PTRACE_SETEVRREGS       21
-#endif
+#ifndef __powerpc64__
+/* Get/set all the upper 32-bits of the SPE registers, accumulator, and
+ * spefscr, in one go */
+#define PTRACE_GETEVRREGS	20
+#define PTRACE_SETEVRREGS	21
+#endif /* __powerpc64__ */
 
 /*
  * Get or set a debug register. The first 16 are DABR registers and the
@@ -196,6 +229,7 @@ extern unsigned long profile_pc(struct pt_regs *regs);
 #define PTRACE_GET_DEBUGREG	25
 #define PTRACE_SET_DEBUGREG	26
 
+#ifdef __powerpc64__
 /* Additional PTRACE requests implemented on PowerPC. */
 #define PPC_PTRACE_GETREGS	0x99	/* Get GPRs 0 - 31 */
 #define PPC_PTRACE_SETREGS	0x98	/* Set GPRs 0 - 31 */
@@ -209,5 +243,6 @@ extern unsigned long profile_pc(struct pt_regs *regs);
 #define PPC_PTRACE_POKEDATA_3264 0x92
 #define PPC_PTRACE_PEEKUSR_3264  0x91
 #define PPC_PTRACE_POKEUSR_3264  0x90
+#endif /* __powerpc64__ */
 
-#endif /* _PPC64_PTRACE_H */
+#endif /* _ASM_POWERPC_PTRACE_H */

include/asm-ppc64/sigcontext.h → include/asm-powerpc/sigcontext.h

@@ -1,5 +1,5 @@
-#ifndef _ASM_PPC64_SIGCONTEXT_H
-#define _ASM_PPC64_SIGCONTEXT_H
+#ifndef _ASM_POWERPC_SIGCONTEXT_H
+#define _ASM_POWERPC_SIGCONTEXT_H
 
 /*
  * This program is free software; you can redistribute it and/or
@@ -9,39 +9,44 @@
  */
 #include <linux/compiler.h>
 #include <asm/ptrace.h>
+#ifdef __powerpc64__
 #include <asm/elf.h>
-
+#endif
 
 struct sigcontext {
 	unsigned long	_unused[4];
 	int		signal;
+#ifdef __powerpc64__
 	int		_pad0;
+#endif
 	unsigned long	handler;
 	unsigned long	oldmask;
 	struct pt_regs	__user *regs;
+#ifdef __powerpc64__
 	elf_gregset_t	gp_regs;
 	elf_fpregset_t	fp_regs;
 /*
- * To maintain compatibility with current implementations the sigcontext is 
- * extended by appending a pointer (v_regs) to a quadword type (elf_vrreg_t) 
- * followed by an unstructured (vmx_reserve) field of 69 doublewords.  This 
- * allows the array of vector registers to be quadword aligned independent of 
- * the alignment of the containing sigcontext or ucontext. It is the 
- * responsibility of the code setting the sigcontext to set this pointer to 
- * either NULL (if this processor does not support the VMX feature) or the 
+ * To maintain compatibility with current implementations the sigcontext is
+ * extended by appending a pointer (v_regs) to a quadword type (elf_vrreg_t)
+ * followed by an unstructured (vmx_reserve) field of 69 doublewords.  This
+ * allows the array of vector registers to be quadword aligned independent of
+ * the alignment of the containing sigcontext or ucontext. It is the
+ * responsibility of the code setting the sigcontext to set this pointer to
+ * either NULL (if this processor does not support the VMX feature) or the
  * address of the first quadword within the allocated (vmx_reserve) area.
  *
- * The pointer (v_regs) of vector type (elf_vrreg_t) is type compatible with 
- * an array of 34 quadword entries (elf_vrregset_t).  The entries with 
- * indexes 0-31 contain the corresponding vector registers.  The entry with 
- * index 32 contains the vscr as the last word (offset 12) within the 
- * quadword.  This allows the vscr to be stored as either a quadword (since 
- * it must be copied via a vector register to/from storage) or as a word.  
- * The entry with index 33 contains the vrsave as the first word (offset 0) 
+ * The pointer (v_regs) of vector type (elf_vrreg_t) is type compatible with
+ * an array of 34 quadword entries (elf_vrregset_t).  The entries with
+ * indexes 0-31 contain the corresponding vector registers.  The entry with
+ * index 32 contains the vscr as the last word (offset 12) within the
+ * quadword.  This allows the vscr to be stored as either a quadword (since
+ * it must be copied via a vector register to/from storage) or as a word.
+ * The entry with index 33 contains the vrsave as the first word (offset 0)
  * within the quadword.
  */
 	elf_vrreg_t	__user *v_regs;
 	long		vmx_reserve[ELF_NVRREG+ELF_NVRREG+1];
+#endif
 };
 
-#endif /* _ASM_PPC64_SIGCONTEXT_H */
+#endif /* _ASM_POWERPC_SIGCONTEXT_H */