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yaml
---
r: 180022
b: refs/heads/master
c: 010c108
h: refs/heads/master
v: v3
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David VomLehn authored and Ralf Baechle committed Jan 27, 2010
1 parent 8578728 commit d3bb97c
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Showing 5 changed files with 19 additions and 4 deletions.
2 changes: 1 addition & 1 deletion [refs]
Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: 59dfa2fcaecc39fb88bfa196cb15adca7146867a
refs/heads/master: 010c108d7af708d9e09b83724a058a76803fbc66
1 change: 1 addition & 0 deletions trunk/arch/mips/include/asm/irq.h
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Expand Up @@ -135,6 +135,7 @@ extern void free_irqno(unsigned int irq);
#define CP0_LEGACY_COMPARE_IRQ 7

extern int cp0_compare_irq;
extern int cp0_compare_irq_shift;
extern int cp0_perfcount_irq;

#endif /* _ASM_IRQ_H */
12 changes: 12 additions & 0 deletions trunk/arch/mips/include/asm/mipsregs.h
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Expand Up @@ -405,6 +405,16 @@
#define ST0_CU3 0x80000000
#define ST0_XX 0x80000000 /* MIPS IV naming */

/*
* Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
*
* Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
*/
#define INTCTLB_IPPCI 26
#define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI)
#define INTCTLB_IPTI 29
#define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI)

/*
* Bitfields and bit numbers in the coprocessor 0 cause register.
*
Expand Down Expand Up @@ -434,6 +444,8 @@
#define CAUSEF_IV (_ULCAST_(1) << 23)
#define CAUSEB_CE 28
#define CAUSEF_CE (_ULCAST_(3) << 28)
#define CAUSEB_TI 30
#define CAUSEF_TI (_ULCAST_(1) << 30)
#define CAUSEB_BD 31
#define CAUSEF_BD (_ULCAST_(1) << 31)

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2 changes: 1 addition & 1 deletion trunk/arch/mips/kernel/cevt-r4k.c
Original file line number Diff line number Diff line change
Expand Up @@ -97,7 +97,7 @@ void mips_event_handler(struct clock_event_device *dev)
*/
static int c0_compare_int_pending(void)
{
return (read_c0_cause() >> cp0_compare_irq) & 0x100;
return (read_c0_cause() >> cp0_compare_irq_shift) & (1ul << CAUSEB_IP);
}

/*
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6 changes: 4 additions & 2 deletions trunk/arch/mips/kernel/traps.c
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Expand Up @@ -1403,6 +1403,7 @@ extern void flush_tlb_handlers(void);
* Timer interrupt
*/
int cp0_compare_irq;
int cp0_compare_irq_shift;

/*
* Performance counter IRQ or -1 if shared with timer
Expand Down Expand Up @@ -1493,8 +1494,9 @@ void __cpuinit per_cpu_trap_init(void)
* o read IntCtl.IPPCI to determine the performance counter interrupt
*/
if (cpu_has_mips_r2) {
cp0_compare_irq = (read_c0_intctl() >> 29) & 7;
cp0_perfcount_irq = (read_c0_intctl() >> 26) & 7;
cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
if (cp0_perfcount_irq == cp0_compare_irq)
cp0_perfcount_irq = -1;
} else {
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