---

yaml
---
r: 286842
b: refs/heads/master
c: 286fed4
h: refs/heads/master
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: b6e45f866465f42b53d803b0c574da0fc508a0e9
+refs/heads/master: 286fed412a134e76be55899bc628c6fa59cb70da

trunk/drivers/gpu/drm/i915/i915_drv.c

@@ -603,12 +603,31 @@ static int gen6_do_reset(struct drm_device *dev, u8 flags)
 	int	ret;
 	unsigned long irqflags;
 
-	I915_WRITE(GEN6_GDRST, GEN6_GRDOM_FULL);
-	ret = wait_for((I915_READ(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
-	/* If reset with a user forcewake, try to restore */
+	/* Hold gt_lock across reset to prevent any register access
+	 * with forcewake not set correctly
+	 */
 	spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
+
+	/* Reset the chip */
+
+	/* GEN6_GDRST is not in the gt power well, no need to check
+	 * for fifo space for the write or forcewake the chip for
+	 * the read
+	 */
+	I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
+
+	/* Spin waiting for the device to ack the reset request */
+	ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
+
+	/* If reset with a user forcewake, try to restore, otherwise turn it off */
 	if (dev_priv->forcewake_count)
 		dev_priv->display.force_wake_get(dev_priv);
+	else
+		dev_priv->display.force_wake_put(dev_priv);
+
+	/* Restore fifo count */
+	dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
+
 	spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
 	return ret;
 }