-
Notifications
You must be signed in to change notification settings - Fork 0
Commit
This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository.
- Loading branch information
Arnd Bergmann
committed
Nov 2, 2011
1 parent
9df0ccd
commit d53442c
Showing
1,727 changed files
with
30,519 additions
and
19,882 deletions.
There are no files selected for viewing
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,2 +1,2 @@ | ||
| --- | ||
| refs/heads/master: 76780127914d5dc69a458eda5e471e65a5fd3dc9 | ||
| refs/heads/master: b8df0ea26ac17c9a073f235c7fdfbdd1851b59ea |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,13 @@ | ||
| What: /sys/class/scsi_host/hostX/isci_id | ||
| Date: June 2011 | ||
| Contact: Dave Jiang <dave.jiang@intel.com> | ||
| Description: | ||
| This file contains the enumerated host ID for the Intel | ||
| SCU controller. The Intel(R) C600 Series Chipset SATA/SAS | ||
| Storage Control Unit embeds up to two 4-port controllers in | ||
| a single PCI device. The controllers are enumerated in order | ||
| which usually means the lowest number scsi_host corresponds | ||
| with the first controller, but this association is not | ||
| guaranteed. The 'isci_id' attribute unambiguously identifies | ||
| the controller index: '0' for the first controller, | ||
| '1' for the second. |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,8 @@ | ||
| Calxeda Highbank Platforms Device Tree Bindings | ||
| ----------------------------------------------- | ||
|
|
||
| Boards with Calxeda Cortex-A9 based Highbank SOC shall have the following | ||
| properties. | ||
|
|
||
| Required root node properties: | ||
| - compatible = "calxeda,highbank"; |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,19 @@ | ||
| i.MX51 Babbage Board | ||
| Required root node properties: | ||
| - compatible = "fsl,imx51-babbage", "fsl,imx51"; | ||
|
|
||
| i.MX53 Automotive Reference Design Board | ||
| Required root node properties: | ||
| - compatible = "fsl,imx53-ard", "fsl,imx53"; | ||
|
|
||
| i.MX53 Evaluation Kit | ||
| Required root node properties: | ||
| - compatible = "fsl,imx53-evk", "fsl,imx53"; | ||
|
|
||
| i.MX53 Quick Start Board | ||
| Required root node properties: | ||
| - compatible = "fsl,imx53-qsb", "fsl,imx53"; | ||
|
|
||
| i.MX53 Smart Mobile Reference Design Board | ||
| Required root node properties: | ||
| - compatible = "fsl,imx53-smd", "fsl,imx53"; |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,55 @@ | ||
| * ARM Generic Interrupt Controller | ||
|
|
||
| ARM SMP cores are often associated with a GIC, providing per processor | ||
| interrupts (PPI), shared processor interrupts (SPI) and software | ||
| generated interrupts (SGI). | ||
|
|
||
| Primary GIC is attached directly to the CPU and typically has PPIs and SGIs. | ||
| Secondary GICs are cascaded into the upward interrupt controller and do not | ||
| have PPIs or SGIs. | ||
|
|
||
| Main node required properties: | ||
|
|
||
| - compatible : should be one of: | ||
| "arm,cortex-a9-gic" | ||
| "arm,arm11mp-gic" | ||
| - interrupt-controller : Identifies the node as an interrupt controller | ||
| - #interrupt-cells : Specifies the number of cells needed to encode an | ||
| interrupt source. The type shall be a <u32> and the value shall be 3. | ||
|
|
||
| The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI | ||
| interrupts. | ||
|
|
||
| The 2nd cell contains the interrupt number for the interrupt type. | ||
| SPI interrupts are in the range [0-987]. PPI interrupts are in the | ||
| range [0-15]. | ||
|
|
||
| The 3rd cell is the flags, encoded as follows: | ||
| bits[3:0] trigger type and level flags. | ||
| 1 = low-to-high edge triggered | ||
| 2 = high-to-low edge triggered | ||
| 4 = active high level-sensitive | ||
| 8 = active low level-sensitive | ||
| bits[15:8] PPI interrupt cpu mask. Each bit corresponds to each of | ||
| the 8 possible cpus attached to the GIC. A bit set to '1' indicated | ||
| the interrupt is wired to that CPU. Only valid for PPI interrupts. | ||
|
|
||
| - reg : Specifies base physical address(s) and size of the GIC registers. The | ||
| first region is the GIC distributor register base and size. The 2nd region is | ||
| the GIC cpu interface register base and size. | ||
|
|
||
| Optional | ||
| - interrupts : Interrupt source of the parent interrupt controller. Only | ||
| present on secondary GICs. | ||
|
|
||
| Example: | ||
|
|
||
| intc: interrupt-controller@fff11000 { | ||
| compatible = "arm,cortex-a9-gic"; | ||
| #interrupt-cells = <3>; | ||
| #address-cells = <1>; | ||
| interrupt-controller; | ||
| reg = <0xfff11000 0x1000>, | ||
| <0xfff10100 0x100>; | ||
| }; | ||
|
|
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,44 @@ | ||
| * ARM L2 Cache Controller | ||
|
|
||
| ARM cores often have a separate level 2 cache controller. There are various | ||
| implementations of the L2 cache controller with compatible programming models. | ||
| The ARM L2 cache representation in the device tree should be done as follows: | ||
|
|
||
| Required properties: | ||
|
|
||
| - compatible : should be one of: | ||
| "arm,pl310-cache" | ||
| "arm,l220-cache" | ||
| "arm,l210-cache" | ||
| - cache-unified : Specifies the cache is a unified cache. | ||
| - cache-level : Should be set to 2 for a level 2 cache. | ||
| - reg : Physical base address and size of cache controller's memory mapped | ||
| registers. | ||
|
|
||
| Optional properties: | ||
|
|
||
| - arm,data-latency : Cycles of latency for Data RAM accesses. Specifies 3 cells of | ||
| read, write and setup latencies. Minimum valid values are 1. Controllers | ||
| without setup latency control should use a value of 0. | ||
| - arm,tag-latency : Cycles of latency for Tag RAM accesses. Specifies 3 cells of | ||
| read, write and setup latencies. Controllers without setup latency control | ||
| should use 0. Controllers without separate read and write Tag RAM latency | ||
| values should only use the first cell. | ||
| - arm,dirty-latency : Cycles of latency for Dirty RAMs. This is a single cell. | ||
| - arm,filter-ranges : <start length> Starting address and length of window to | ||
| filter. Addresses in the filter window are directed to the M1 port. Other | ||
| addresses will go to the M0 port. | ||
| - interrupts : 1 combined interrupt. | ||
|
|
||
| Example: | ||
|
|
||
| L2: cache-controller { | ||
| compatible = "arm,pl310-cache"; | ||
| reg = <0xfff12000 0x1000>; | ||
| arm,data-latency = <1 1 1>; | ||
| arm,tag-latency = <2 2 2>; | ||
| arm,filter-latency = <0x80000000 0x8000000>; | ||
| cache-unified; | ||
| cache-level = <2>; | ||
| interrupts = <45>; | ||
| }; |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,14 @@ | ||
| * TI - DSP (Digital Signal Processor) | ||
|
|
||
| TI DSP included in OMAP SoC | ||
|
|
||
| Required properties: | ||
| - compatible : Should be "ti,omap3-c64" for OMAP3 & 4 | ||
| - ti,hwmods: "dsp" | ||
|
|
||
| Examples: | ||
|
|
||
| dsp { | ||
| compatible = "ti,omap3-c64"; | ||
| ti,hwmods = "dsp"; | ||
| }; |
Oops, something went wrong.