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Merge master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6
* master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6: sh: Fix stacktrace simplification fallout. sh: SH7760 DMABRG support. sh: clockevent/clocksource/hrtimers/nohz TMU support. sh: Truncate MAX_ACTIVE_REGIONS for the common case. rtc: rtc-sh: Fix rtc_dev pointer for rtc_update_irq(). sh: Convert to common die chain. sh: Wire up utimensat syscall. sh: landisk mv_nr_irqs definition. sh: Fixup ndelay() xloops calculation for alternate HZ. sh: Add 32-bit opcode feature CPU flag. sh: Fix PC adjustments for varying opcode length. sh: Support for SH-2A 32-bit opcodes. sh: Kill off redundant __div64_32 symbol export. sh: Share exception vector table for SH-3/4. sh: Always define TRAPA_BUG_OPCODE. sh: __GFP_REPEAT for pte allocations, too. rtc: rtc-sh: Fix up dev_dbg() warnings. sh: generic quicklist support.
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,196 @@ | ||
| /* | ||
| * SH7760 DMABRG IRQ handling | ||
| * | ||
| * (c) 2007 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com> | ||
| * licensed under the GPLv2. | ||
| * | ||
| */ | ||
|
|
||
| #include <linux/interrupt.h> | ||
| #include <linux/kernel.h> | ||
| #include <asm/dma.h> | ||
| #include <asm/dmabrg.h> | ||
| #include <asm/io.h> | ||
|
|
||
| /* | ||
| * The DMABRG is a special DMA unit within the SH7760. It does transfers | ||
| * from USB-SRAM/Audio units to main memory (and also the LCDC; but that | ||
| * part is sensibly placed in the LCDC registers and requires no irqs) | ||
| * It has 3 IRQ lines which trigger 10 events, and works independently | ||
| * from the traditional SH DMAC (although it blocks usage of DMAC 0) | ||
| * | ||
| * BRGIRQID | component | dir | meaning | source | ||
| * ----------------------------------------------------- | ||
| * 0 | USB-DMA | ... | xfer done | DMABRGI1 | ||
| * 1 | USB-UAE | ... | USB addr err.| DMABRGI0 | ||
| * 2 | HAC0/SSI0 | play| all done | DMABRGI1 | ||
| * 3 | HAC0/SSI0 | play| half done | DMABRGI2 | ||
| * 4 | HAC0/SSI0 | rec | all done | DMABRGI1 | ||
| * 5 | HAC0/SSI0 | rec | half done | DMABRGI2 | ||
| * 6 | HAC1/SSI1 | play| all done | DMABRGI1 | ||
| * 7 | HAC1/SSI1 | play| half done | DMABRGI2 | ||
| * 8 | HAC1/SSI1 | rec | all done | DMABRGI1 | ||
| * 9 | HAC1/SSI1 | rec | half done | DMABRGI2 | ||
| * | ||
| * all can be enabled/disabled in the DMABRGCR register, | ||
| * as well as checked if they occured. | ||
| * | ||
| * DMABRGI0 services USB DMA Address errors, but it still must be | ||
| * enabled/acked in the DMABRGCR register. USB-DMA complete indicator | ||
| * is grouped together with the audio buffer end indicators, too bad... | ||
| * | ||
| * DMABRGCR: Bits 31-24: audio-dma ENABLE flags, | ||
| * Bits 23-16: audio-dma STATUS flags, | ||
| * Bits 9-8: USB error/xfer ENABLE, | ||
| * Bits 1-0: USB error/xfer STATUS. | ||
| * Ack an IRQ by writing 0 to the STATUS flag. | ||
| * Mask IRQ by writing 0 to ENABLE flag. | ||
| * | ||
| * Usage is almost like with any other IRQ: | ||
| * dmabrg_request_irq(BRGIRQID, handler, data) | ||
| * dmabrg_free_irq(BRGIRQID) | ||
| * | ||
| * handler prototype: void brgirqhandler(void *data) | ||
| */ | ||
|
|
||
| #define DMARSRA 0xfe090000 | ||
| #define DMAOR 0xffa00040 | ||
| #define DMACHCR0 0xffa0000c | ||
| #define DMABRGCR 0xfe3c0000 | ||
|
|
||
| #define DMAOR_BRG 0x0000c000 | ||
| #define DMAOR_DMEN 0x00000001 | ||
|
|
||
| #define DMABRGI0 68 | ||
| #define DMABRGI1 69 | ||
| #define DMABRGI2 70 | ||
|
|
||
| struct dmabrg_handler { | ||
| void (*handler)(void *); | ||
| void *data; | ||
| } *dmabrg_handlers; | ||
|
|
||
| static inline void dmabrg_call_handler(int i) | ||
| { | ||
| dmabrg_handlers[i].handler(dmabrg_handlers[i].data); | ||
| } | ||
|
|
||
| /* | ||
| * main DMABRG irq handler. It acks irqs and then | ||
| * handles every set and unmasked bit sequentially. | ||
| * No locking and no validity checks; it should be | ||
| * as fast as possible (audio!) | ||
| */ | ||
| static irqreturn_t dmabrg_irq(int irq, void *data) | ||
| { | ||
| unsigned long dcr; | ||
| unsigned int i; | ||
|
|
||
| dcr = ctrl_inl(DMABRGCR); | ||
| ctrl_outl(dcr & ~0x00ff0003, DMABRGCR); /* ack all */ | ||
| dcr &= dcr >> 8; /* ignore masked */ | ||
|
|
||
| /* USB stuff, get it out of the way first */ | ||
| if (dcr & 1) | ||
| dmabrg_call_handler(DMABRGIRQ_USBDMA); | ||
| if (dcr & 2) | ||
| dmabrg_call_handler(DMABRGIRQ_USBDMAERR); | ||
|
|
||
| /* Audio */ | ||
| dcr >>= 16; | ||
| while (dcr) { | ||
| i = __ffs(dcr); | ||
| dcr &= dcr - 1; | ||
| dmabrg_call_handler(i + DMABRGIRQ_A0TXF); | ||
| } | ||
| return IRQ_HANDLED; | ||
| } | ||
|
|
||
| static void dmabrg_disable_irq(unsigned int dmairq) | ||
| { | ||
| unsigned long dcr; | ||
| dcr = ctrl_inl(DMABRGCR); | ||
| dcr &= ~(1 << ((dmairq > 1) ? dmairq + 22 : dmairq + 8)); | ||
| ctrl_outl(dcr, DMABRGCR); | ||
| } | ||
|
|
||
| static void dmabrg_enable_irq(unsigned int dmairq) | ||
| { | ||
| unsigned long dcr; | ||
| dcr = ctrl_inl(DMABRGCR); | ||
| dcr |= (1 << ((dmairq > 1) ? dmairq + 22 : dmairq + 8)); | ||
| ctrl_outl(dcr, DMABRGCR); | ||
| } | ||
|
|
||
| int dmabrg_request_irq(unsigned int dmairq, void(*handler)(void*), | ||
| void *data) | ||
| { | ||
| if ((dmairq > 9) || !handler) | ||
| return -ENOENT; | ||
| if (dmabrg_handlers[dmairq].handler) | ||
| return -EBUSY; | ||
|
|
||
| dmabrg_handlers[dmairq].handler = handler; | ||
| dmabrg_handlers[dmairq].data = data; | ||
|
|
||
| dmabrg_enable_irq(dmairq); | ||
| return 0; | ||
| } | ||
| EXPORT_SYMBOL_GPL(dmabrg_request_irq); | ||
|
|
||
| void dmabrg_free_irq(unsigned int dmairq) | ||
| { | ||
| if (likely(dmairq < 10)) { | ||
| dmabrg_disable_irq(dmairq); | ||
| dmabrg_handlers[dmairq].handler = NULL; | ||
| dmabrg_handlers[dmairq].data = NULL; | ||
| } | ||
| } | ||
| EXPORT_SYMBOL_GPL(dmabrg_free_irq); | ||
|
|
||
| static int __init dmabrg_init(void) | ||
| { | ||
| unsigned long or; | ||
| int ret; | ||
|
|
||
| dmabrg_handlers = kzalloc(10 * sizeof(struct dmabrg_handler), | ||
| GFP_KERNEL); | ||
| if (!dmabrg_handlers) | ||
| return -ENOMEM; | ||
|
|
||
| #ifdef CONFIG_SH_DMA | ||
| /* request DMAC channel 0 before anyone else can get it */ | ||
| ret = request_dma(0, "DMAC 0 (DMABRG)"); | ||
| if (ret < 0) | ||
| printk(KERN_INFO "DMABRG: DMAC ch0 not reserved!\n"); | ||
| #endif | ||
|
|
||
| ctrl_outl(0, DMABRGCR); | ||
| ctrl_outl(0, DMACHCR0); | ||
| ctrl_outl(0x94000000, DMARSRA); /* enable DMABRG in DMAC 0 */ | ||
|
|
||
| /* enable DMABRG mode, enable the DMAC */ | ||
| or = ctrl_inl(DMAOR); | ||
| ctrl_outl(or | DMAOR_BRG | DMAOR_DMEN, DMAOR); | ||
|
|
||
| ret = request_irq(DMABRGI0, dmabrg_irq, IRQF_DISABLED, | ||
| "DMABRG USB address error", NULL); | ||
| if (ret) | ||
| goto out0; | ||
|
|
||
| ret = request_irq(DMABRGI1, dmabrg_irq, IRQF_DISABLED, | ||
| "DMABRG Transfer End", NULL); | ||
| if (ret) | ||
| goto out1; | ||
|
|
||
| ret = request_irq(DMABRGI2, dmabrg_irq, IRQF_DISABLED, | ||
| "DMABRG Transfer Half", NULL); | ||
| if (ret == 0) | ||
| return ret; | ||
|
|
||
| free_irq(DMABRGI1, 0); | ||
| out1: free_irq(DMABRGI0, 0); | ||
| out0: kfree(dmabrg_handlers); | ||
| return ret; | ||
| } | ||
| subsys_initcall(dmabrg_init); |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,55 @@ | ||
| /* | ||
| * arch/sh/kernel/cpu/sh2a/opcode_helper.c | ||
| * | ||
| * Helper for the SH-2A 32-bit opcodes. | ||
| * | ||
| * Copyright (C) 2007 Paul Mundt | ||
| * | ||
| * This file is subject to the terms and conditions of the GNU General Public | ||
| * License. See the file "COPYING" in the main directory of this archive | ||
| * for more details. | ||
| */ | ||
| #include <linux/kernel.h> | ||
| #include <asm/system.h> | ||
|
|
||
| /* | ||
| * Instructions on SH are generally fixed at 16-bits, however, SH-2A | ||
| * introduces some 32-bit instructions. Since there are no real | ||
| * constraints on their use (and they can be mixed and matched), we need | ||
| * to check the instruction encoding to work out if it's a true 32-bit | ||
| * instruction or not. | ||
| * | ||
| * Presently, 32-bit opcodes have only slight variations in what the | ||
| * actual encoding looks like in the first-half of the instruction, which | ||
| * makes it fairly straightforward to differentiate from the 16-bit ones. | ||
| * | ||
| * First 16-bits of encoding Used by | ||
| * | ||
| * 0011nnnnmmmm0001 mov.b, mov.w, mov.l, fmov.d, | ||
| * fmov.s, movu.b, movu.w | ||
| * | ||
| * 0011nnnn0iii1001 bclr.b, bld.b, bset.b, bst.b, band.b, | ||
| * bandnot.b, bldnot.b, bor.b, bornot.b, | ||
| * bxor.b | ||
| * | ||
| * 0000nnnniiii0000 movi20 | ||
| * 0000nnnniiii0001 movi20s | ||
| */ | ||
| unsigned int instruction_size(unsigned int insn) | ||
| { | ||
| /* Look for the common cases */ | ||
| switch ((insn & 0xf00f)) { | ||
| case 0x0000: /* movi20 */ | ||
| case 0x0001: /* movi20s */ | ||
| case 0x3001: /* 32-bit mov/fmov/movu variants */ | ||
| return 4; | ||
| } | ||
|
|
||
| /* And the special cases.. */ | ||
| switch ((insn & 0xf08f)) { | ||
| case 0x3009: /* 32-bit b*.b bit operations */ | ||
| return 4; | ||
| } | ||
|
|
||
| return 2; | ||
| } |
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