---

yaml
---
r: 145855
b: refs/heads/master
c: be15f9d
h: refs/heads/master
i:
  145853: 882f55b
  145851: c3348e0
  145847: 57b9c9c
  145839: 8289d9a
  145823: c51f7e3
  145791: 6675e3a
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: a789ed5fb6d0256c4177c2cc27e06520ddbe4d4c
+refs/heads/master: be15f9d63b97da0065187696962331de6cd9de9e

trunk/Documentation/ABI/testing/sysfs-devices-cache_disable

@@ -0,0 +1,18 @@
+What:      /sys/devices/system/cpu/cpu*/cache/index*/cache_disable_X
+Date:      August 2008
+KernelVersion:	2.6.27
+Contact:	mark.langsdorf@amd.com
+Description:	These files exist in every cpu's cache index directories.
+		There are currently 2 cache_disable_# files in each
+		directory.  Reading from these files on a supported
+		processor will return that cache disable index value
+		for that processor and node.  Writing to one of these
+		files will cause the specificed cache index to be disabled.
+
+		Currently, only AMD Family 10h Processors support cache index
+		disable, and only for their L3 caches.  See the BIOS and
+		Kernel Developer's Guide at
+		http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/31116-Public-GH-BKDG_3.20_2-4-09.pdf
+		for formatting information and other details on the
+		cache index disable.
+Users:    joachim.deguara@amd.com