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yaml --- r: 191803 b: refs/heads/master c: ba02a21 h: refs/heads/master i: 191801: 2e59365 191799: 84a369c v: v3
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Russell King
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Apr 29, 2010
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--- | ||
refs/heads/master: a285edcf18b8838814d645c7e411a337a825236e | ||
refs/heads/master: ba02a21544b41a65e58506f1d79353203d94b8b6 |
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#ifndef __ASM_ARM_HARDWARE_ARM_TIMER_H | ||
#define __ASM_ARM_HARDWARE_ARM_TIMER_H | ||
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#define TIMER_LOAD 0x00 | ||
#define TIMER_VALUE 0x04 | ||
#define TIMER_CTRL 0x08 | ||
#define TIMER_CTRL_ONESHOT (1 << 0) | ||
#define TIMER_CTRL_32BIT (1 << 1) | ||
#define TIMER_CTRL_DIV1 (0 << 2) | ||
#define TIMER_CTRL_DIV16 (1 << 2) | ||
#define TIMER_CTRL_DIV256 (2 << 2) | ||
#define TIMER_CTRL_IE (1 << 5) /* Interrupt Enable (versatile only) */ | ||
#define TIMER_CTRL_PERIODIC (1 << 6) | ||
#define TIMER_CTRL_ENABLE (1 << 7) | ||
/* | ||
* ARM timer implementation, found in Integrator, Versatile and Realview | ||
* platforms. Not all platforms support all registers and bits in these | ||
* registers, so we mark them with A for Integrator AP, C for Integrator | ||
* CP, V for Versatile and R for Realview. | ||
* | ||
* Integrator AP has 16-bit timers, Integrator CP, Versatile and Realview | ||
* can have 16-bit or 32-bit selectable via a bit in the control register. | ||
*/ | ||
#define TIMER_LOAD 0x00 /* ACVR rw */ | ||
#define TIMER_VALUE 0x04 /* ACVR ro */ | ||
#define TIMER_CTRL 0x08 /* ACVR rw */ | ||
#define TIMER_CTRL_ONESHOT (1 << 0) /* CVR */ | ||
#define TIMER_CTRL_32BIT (1 << 1) /* CVR */ | ||
#define TIMER_CTRL_DIV1 (0 << 2) /* ACVR */ | ||
#define TIMER_CTRL_DIV16 (1 << 2) /* ACVR */ | ||
#define TIMER_CTRL_DIV256 (2 << 2) /* ACVR */ | ||
#define TIMER_CTRL_IE (1 << 5) /* VR */ | ||
#define TIMER_CTRL_PERIODIC (1 << 6) /* ACVR */ | ||
#define TIMER_CTRL_ENABLE (1 << 7) /* ACVR */ | ||
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#define TIMER_INTCLR 0x0c | ||
#define TIMER_RIS 0x10 | ||
#define TIMER_MIS 0x14 | ||
#define TIMER_BGLOAD 0x18 | ||
#define TIMER_INTCLR 0x0c /* ACVR wo */ | ||
#define TIMER_RIS 0x10 /* CVR ro */ | ||
#define TIMER_MIS 0x14 /* CVR ro */ | ||
#define TIMER_BGLOAD 0x18 /* CVR rw */ | ||
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#endif |