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r: 310865
b: refs/heads/master
c: f2bf1f6
h: refs/heads/master
i:
  310863: b45991e
v: v3
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Steven Rostedt authored and Steven Rostedt committed Jun 7, 2012
1 parent 6d30d25 commit dc93114
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2 changes: 1 addition & 1 deletion [refs]
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---
refs/heads/master: a95f9b6e092ed862278e08266207c7ab231076b4
refs/heads/master: f2bf1f6f5f89d031245067512449fc889b2f4bb2
93 changes: 0 additions & 93 deletions trunk/Documentation/devicetree/bindings/i2c/i2c-mux-pinctrl.txt

This file was deleted.

9 changes: 0 additions & 9 deletions trunk/Documentation/kernel-parameters.txt
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Expand Up @@ -2543,15 +2543,6 @@ bytes respectively. Such letter suffixes can also be entirely omitted.

sched_debug [KNL] Enables verbose scheduler debug messages.

skew_tick= [KNL] Offset the periodic timer tick per cpu to mitigate
xtime_lock contention on larger systems, and/or RCU lock
contention on all systems with CONFIG_MAXSMP set.
Format: { "0" | "1" }
0 -- disable. (may be 1 via CONFIG_CMDLINE="skew_tick=1"
1 -- enable.
Note: increases power consumption, thus should only be
enabled if running jitter sensitive (HPC/RT) workloads.

security= [SECURITY] Choose a security module to enable at boot.
If this boot parameter is not specified, only the first
security module asking for security registration will be
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44 changes: 19 additions & 25 deletions trunk/Documentation/networking/stmmac.txt
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Expand Up @@ -10,8 +10,8 @@ Currently this network device driver is for all STM embedded MAC/GMAC
(i.e. 7xxx/5xxx SoCs), SPEAr (arm), Loongson1B (mips) and XLINX XC2V3000
FF1152AMT0221 D1215994A VIRTEX FPGA board.

DWC Ether MAC 10/100/1000 Universal version 3.60a (and older) and DWC Ether
MAC 10/100 Universal version 4.0 have been used for developing this driver.
DWC Ether MAC 10/100/1000 Universal version 3.60a (and older) and DWC Ether MAC 10/100
Universal version 4.0 have been used for developing this driver.

This driver supports both the platform bus and PCI.

Expand Down Expand Up @@ -54,27 +54,27 @@ net_device structure enabling the scatter/gather feature.
When one or more packets are received, an interrupt happens. The interrupts
are not queued so the driver has to scan all the descriptors in the ring during
the receive process.
This is based on NAPI so the interrupt handler signals only if there is work
to be done, and it exits.
This is based on NAPI so the interrupt handler signals only if there is work to be
done, and it exits.
Then the poll method will be scheduled at some future point.
The incoming packets are stored, by the DMA, in a list of pre-allocated socket
buffers in order to avoid the memcpy (Zero-copy).

4.3) Timer-Driver Interrupt
Instead of having the device that asynchronously notifies the frame receptions,
the driver configures a timer to generate an interrupt at regular intervals.
Based on the granularity of the timer, the frames that are received by the
device will experience different levels of latency. Some NICs have dedicated
timer device to perform this task. STMMAC can use either the RTC device or the
TMU channel 2 on STLinux platforms.
Instead of having the device that asynchronously notifies the frame receptions, the
driver configures a timer to generate an interrupt at regular intervals.
Based on the granularity of the timer, the frames that are received by the device
will experience different levels of latency. Some NICs have dedicated timer
device to perform this task. STMMAC can use either the RTC device or the TMU
channel 2 on STLinux platforms.
The timers frequency can be passed to the driver as parameter; when change it,
take care of both hardware capability and network stability/performance impact.
Several performance tests on STM platforms showed this optimisation allows to
spare the CPU while having the maximum throughput.
Several performance tests on STM platforms showed this optimisation allows to spare
the CPU while having the maximum throughput.

4.4) WOL
Wake up on Lan feature through Magic and Unicast frames are supported for the
GMAC core.
Wake up on Lan feature through Magic and Unicast frames are supported for the GMAC
core.

4.5) DMA descriptors
Driver handles both normal and enhanced descriptors. The latter has been only
Expand Down Expand Up @@ -106,8 +106,7 @@ Several driver's information can be passed through the platform
These are included in the include/linux/stmmac.h header file
and detailed below as well:

struct plat_stmmacenet_data {
char *phy_bus_name;
struct plat_stmmacenet_data {
int bus_id;
int phy_addr;
int interface;
Expand All @@ -125,24 +124,19 @@ struct plat_stmmacenet_data {
void (*bus_setup)(void __iomem *ioaddr);
int (*init)(struct platform_device *pdev);
void (*exit)(struct platform_device *pdev);
void *custom_cfg;
void *custom_data;
void *bsp_priv;
};

Where:
o phy_bus_name: phy bus name to attach to the stmmac.
o bus_id: bus identifier.
o phy_addr: the physical address can be passed from the platform.
If it is set to -1 the driver will automatically
detect it at run-time by probing all the 32 addresses.
o interface: PHY device's interface.
o mdio_bus_data: specific platform fields for the MDIO bus.
o dma_cfg: internal DMA parameters
o pbl: the Programmable Burst Length is maximum number of beats to
o pbl: the Programmable Burst Length is maximum number of beats to
be transferred in one DMA transaction.
GMAC also enables the 4xPBL by default.
o fixed_burst/mixed_burst/burst_len
o clk_csr: fixed CSR Clock range selection.
o has_gmac: uses the GMAC core.
o enh_desc: if sets the MAC will use the enhanced descriptor structure.
Expand All @@ -166,9 +160,8 @@ Where:
this is sometime necessary on some platforms (e.g. ST boxes)
where the HW needs to have set some PIO lines or system cfg
registers.
o custom_cfg/custom_data: this is a custom configuration that can be passed
while initialising the resources.
o bsp_priv: another private poiter.
o custom_cfg: this is a custom configuration that can be passed while
initialising the resources.

For MDIO bus The we have:

Expand All @@ -187,6 +180,7 @@ Where:
o irqs: list of IRQs, one per PHY.
o probed_phy_irq: if irqs is NULL, use this for probed PHY.


For DMA engine we have the following internal fields that should be
tuned according to the HW capabilities.

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