ALSA: Fix for reading RIRB buffer on NVIDIA aza controller with AMD P…

…henom cpu

When read RIRB buffer immediately after RIRB interrupt received,
sometimes the data will be "0x0". If we wait for some time, the data
in buffer will be correct. This issue only occurred with AMD Phenom cpu.
So we set this "needs_damn_long_delay" flag.

Signed-off-by: Wei Ni <wni@nvidia.com>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
Signed-off-by: Jaroslav Kysela <perex@perex.cz>

sound/pci/hda/hda_intel.c

@@ -1220,6 +1220,9 @@ static int __devinit azx_codec_create(struct azx *chip, const char *model,
 	if (err < 0)
 		return err;
 
+	if (chip->driver_type == AZX_DRIVER_NVIDIA)
+		chip->bus->needs_damn_long_delay = 1;
+
 	codecs = audio_codecs = 0;
 	max_slots = azx_max_codecs[chip->driver_type];
 	if (!max_slots)