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ath9k_hw: Read and configure turnning caps to regulate freq accuracy
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Right now it is done for only AR9485, will be done for ar9003 also
after proper testing.

Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
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Vasanthakumar Thiagarajan authored and John W. Linville committed Dec 7, 2010
1 parent ab09b5b commit dd040f7
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Showing 2 changed files with 22 additions and 0 deletions.
16 changes: 16 additions & 0 deletions drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
Original file line number Diff line number Diff line change
Expand Up @@ -3737,6 +3737,20 @@ static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)

}

static void ar9003_hw_apply_tuning_caps(struct ath_hw *ah)
{
struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
u8 tuning_caps_param = eep->baseEepHeader.params_for_tuning_caps[0];

if (eep->baseEepHeader.featureEnable & 0x40) {
tuning_caps_param &= 0x7f;
REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPINDAC,
tuning_caps_param);
REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPOUTDAC,
tuning_caps_param);
}
}

static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
struct ath9k_channel *chan)
{
Expand All @@ -3745,6 +3759,8 @@ static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
ar9003_hw_drive_strength_apply(ah);
ar9003_hw_atten_apply(ah, chan);
ar9003_hw_internal_regulator_apply(ah);
if (AR_SREV_9485(ah))
ar9003_hw_apply_tuning_caps(ah);
}

static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah,
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6 changes: 6 additions & 0 deletions drivers/net/wireless/ath/ath9k/ar9003_phy.h
Original file line number Diff line number Diff line change
Expand Up @@ -598,6 +598,12 @@
#define AR_CH0_TOP2_XPABIASLVL 0xf000
#define AR_CH0_TOP2_XPABIASLVL_S 12

#define AR_CH0_XTAL (AR_SREV_9485(ah) ? 0x16290 : 0x16294)
#define AR_CH0_XTAL_CAPINDAC 0x7f000000
#define AR_CH0_XTAL_CAPINDAC_S 24
#define AR_CH0_XTAL_CAPOUTDAC 0x00fe0000
#define AR_CH0_XTAL_CAPOUTDAC_S 17

#define AR_PHY_PMU1 0x16c40
#define AR_PHY_PMU1_PWD 0x1
#define AR_PHY_PMU1_PWD_S 0
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