---

yaml --- r: 62652 b: refs/heads/master c: 7092fc3 h: refs/heads/master v: v3
git-mirror · Jul 20, 2007 · dd335c3 · dd335c3
1 parent bb26663
commit dd335c3
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Showing 3 changed files with 1 addition and 17 deletions.
diff --git a/[refs] b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 69ebb22277a53f612ccd632ceb73ed87c9093412
+refs/heads/master: 7092fc38ee770251aed361572bf6bed05fcf3ee2
diff --git a/trunk/arch/arm/mm/Kconfig b/trunk/arch/arm/mm/Kconfig
@@ -612,12 +612,6 @@ config CPU_CACHE_ROUND_ROBIN
 	  Say Y here to use the predictable round-robin cache replacement
 	  policy.  Unless you specifically require this or are unsure, say N.
 
-config CPU_L2CACHE_DISABLE
-	bool "Disable level 2 cache"
-	depends on CPU_V7
-	help
-	  Say Y here to disable the level 2 cache.  If unsure, say N.
-
 config CPU_BPREDICT_DISABLE
 	bool "Disable branch prediction"
 	depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3 || CPU_V7

diff --git a/trunk/arch/arm/mm/proc-v7.S b/trunk/arch/arm/mm/proc-v7.S
@@ -176,16 +176,6 @@ __v7_setup:
 	mcr	p15, 0, r4, c2, c0, 1		@ load TTB1
 	mov	r10, #0x1f			@ domains 0, 1 = manager
 	mcr	p15, 0, r10, c3, c0, 0		@ load domain access register
-#ifndef CONFIG_CPU_L2CACHE_DISABLE
-	@ L2 cache configuration in the L2 aux control register
-	mrc	p15, 1, r10, c9, c0, 2
-	bic	r10, r10, #(1 << 16)		@ L2 outer cache
-	mcr	p15, 1, r10, c9, c0, 2
-	@ L2 cache is enabled in the aux control register
-	mrc	p15, 0, r10, c1, c0, 1
-	orr	r10, r10, #2
-	mcr	p15, 0, r10, c1, c0, 1
-#endif
 	mrc	p15, 0, r0, c1, c0, 0		@ read control register
 	ldr	r10, cr1_clear			@ get mask for bits to clear
 	bic	r0, r0, r10			@ clear bits them