---

yaml
---
r: 123730
b: refs/heads/master
c: e031ab2
h: refs/heads/master
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 3ff164e15574191c69e8406794b0578c8d2a4e23
+refs/heads/master: e031ab23deb5a5d9ac5744e69a0627823e81b074

trunk/arch/arm/plat-omap/gpio.c

@@ -245,6 +245,8 @@ static inline struct gpio_bank *get_gpio_bank(int gpio)
 		return &gpio_bank[gpio >> 5];
 	if (cpu_is_omap34xx())
 		return &gpio_bank[gpio >> 5];
+	BUG();
+	return NULL;
 }
 
 static inline int get_gpio_index(int gpio)
@@ -448,28 +450,36 @@ void omap_set_gpio_debounce(int gpio, int enable)
 {
 	struct gpio_bank *bank;
 	void __iomem *reg;
+	unsigned long flags;
 	u32 val, l = 1 << get_gpio_index(gpio);
 
 	if (cpu_class_is_omap1())
 		return;
 
 	bank = get_gpio_bank(gpio);
 	reg = bank->base;
-
 	reg += OMAP24XX_GPIO_DEBOUNCE_EN;
+
+	spin_lock_irqsave(&bank->lock, flags);
 	val = __raw_readl(reg);
 
 	if (enable && !(val & l))
 		val |= l;
-	else if (!enable && val & l)
+	else if (!enable && (val & l))
 		val &= ~l;
 	else
-		return;
+		goto done;
 
-	if (cpu_is_omap34xx())
-		enable ? clk_enable(bank->dbck) : clk_disable(bank->dbck);
+	if (cpu_is_omap34xx()) {
+		if (enable)
+			clk_enable(bank->dbck);
+		else
+			clk_disable(bank->dbck);
+	}
 
 	__raw_writel(val, reg);
+done:
+	spin_unlock_irqrestore(&bank->lock, flags);
 }
 EXPORT_SYMBOL(omap_set_gpio_debounce);