[ARM] mmp2: add handling on PMIC IRQ

Since PMIC INT pin is a special pin of CPU, the status of PMIC INT pin needs
to be cleared after PMIC IRQ occured. Now append the clear operation in
irq chip handler.

Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>

arch/arm/mach-mmp/common.h

@@ -3,6 +3,7 @@
 struct sys_timer;
 
 extern void timer_init(int irq);
+extern void mmp2_clear_pmic_int(void);
 
 extern struct sys_timer pxa168_timer;
 extern struct sys_timer pxa910_timer;

arch/arm/mach-mmp/irq-mmp2.c

@@ -42,6 +42,12 @@ static struct irq_chip icu_irq_chip = {
 	.unmask		= icu_unmask_irq,
 };
 
+static void pmic_irq_ack(unsigned int irq)
+{
+	if (irq == IRQ_MMP2_PMIC)
+		mmp2_clear_pmic_int();
+}
+
 #define SECOND_IRQ_MASK(_name_, irq_base, prefix)			\
 static void _name_##_mask_irq(unsigned int irq)				\
 {									\
@@ -82,7 +88,6 @@ SECOND_IRQ_DEMUX(_name_, irq_base, prefix)				\
 static struct irq_chip _name_##_irq_chip = {				\
 	.name		= #_name_,					\
 	.mask		= _name_##_mask_irq,				\
-	.mask_ack	= _name_##_mask_irq,				\
 	.unmask		= _name_##_unmask_irq,				\
 }
 
@@ -126,6 +131,11 @@ void __init mmp2_init_icu(void)
 		}
 	}
 
+	/* NOTE: IRQ_MMP2_PMIC requires the PMIC MFPR register
+	 * to be written to clear the interrupt
+	 */
+	pmic_irq_chip.ack = pmic_irq_ack;
+
 	init_mux_irq(&pmic_irq_chip, IRQ_MMP2_PMIC_BASE, 2);
 	init_mux_irq(&rtc_irq_chip, IRQ_MMP2_RTC_BASE, 2);
 	init_mux_irq(&twsi_irq_chip, IRQ_MMP2_TWSI_BASE, 5);

arch/arm/mach-mmp/mmp2.c

@@ -37,6 +37,16 @@ static struct mfp_addr_map mmp2_addr_map[] __initdata = {
 	MFP_ADDR_END,
 };
 
+void mmp2_clear_pmic_int(void)
+{
+	unsigned long mfpr_pmic, data;
+
+	mfpr_pmic = APB_VIRT_BASE + 0x1e000 + 0x2c4;
+	data = __raw_readl(mfpr_pmic);
+	__raw_writel(data | (1 << 6), mfpr_pmic);
+	__raw_writel(data, mfpr_pmic);
+}
+
 static void __init mmp2_init_gpio(void)
 {
 	int i;