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[POWERPC] mpc82xx: Update mpc8272ads, and factor out PCI and reset.
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1. PCI and reset are factored out into pq2.c.  I renamed them from m82xx
to pq2 because they won't work on the Integrated Host Processor line of
82xx chips (i.e. 8240, 8245, and such).

2. The PCI PIC, which is nominally board-specific, is used on multiple
boards, and thus is used into pq2ads-pci-pic.c.

3. The new CPM binding is used.

4. General cleanup.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Scott Wood authored and Kumar Gala committed Oct 4, 2007
1 parent 11c146c commit e00c549
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Showing 10 changed files with 757 additions and 776 deletions.
2 changes: 1 addition & 1 deletion arch/powerpc/Kconfig
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Original file line number Diff line number Diff line change
Expand Up @@ -484,7 +484,7 @@ config PCI_8260

config 8260_PCI9
bool "Enable workaround for MPC826x erratum PCI 9"
depends on PCI_8260 && !ADS8272
depends on PCI_8260 && !8272
default y

choice
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309 changes: 167 additions & 142 deletions arch/powerpc/boot/dts/mpc8272ads.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@

/ {
model = "MPC8272ADS";
compatible = "MPC8260ADS";
compatible = "fsl,mpc8272ads";
#address-cells = <1>;
#size-cells = <1>;

Expand All @@ -22,192 +22,217 @@
PowerPC,8272@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <20>; // 32 bytes
i-cache-line-size = <20>; // 32 bytes
d-cache-size = <4000>; // L1, 16K
i-cache-size = <4000>; // L1, 16K
d-cache-line-size = <d#32>;
i-cache-line-size = <d#32>;
d-cache-size = <d#16384>;
i-cache-size = <d#16384>;
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
};
};

pci_pic: interrupt-controller@f8200000 {
#address-cells = <0>;
#interrupt-cells = <2>;
interrupt-controller;
reg = <f8200000 f8200004>;
device_type = "pci-pic";
};

memory {
device_type = "memory";
reg = <00000000 4000000 f4500000 00000020>;
};

chosen {
name = "chosen";
linux,platform = <0>;
interrupt-controller = <&Cpm_pic>;
reg = <0 0>;
};

soc8272@f0000000 {
#address-cells = <1>;
localbus@f0010100 {
compatible = "fsl,mpc8272-localbus",
"fsl,pq2-localbus";
#address-cells = <2>;
#size-cells = <1>;
device_type = "soc";
ranges = <00000000 f0000000 00053000>;
reg = <f0000000 10000>;
reg = <f0010100 40>;

mdio@0 {
device_type = "mdio";
compatible = "fs_enet";
reg = <0 0>;
#address-cells = <1>;
#size-cells = <0>;

phy0:ethernet-phy@0 {
interrupt-parent = <&Cpm_pic>;
interrupts = <17 4>;
reg = <0>;
bitbang = [ 12 12 13 02 02 01 ];
device_type = "ethernet-phy";
};
ranges = <0 0 fe000000 02000000
1 0 f4500000 00008000
3 0 f8200000 00008000>;

phy1:ethernet-phy@1 {
interrupt-parent = <&Cpm_pic>;
interrupts = <17 4>;
bitbang = [ 12 12 13 02 02 01 ];
reg = <3>;
device_type = "ethernet-phy";
};
flash@0,0 {
compatible = "jedec-flash";
reg = <0 0 2000000>;
bank-width = <4>;
device-width = <1>;
};

ethernet@24000 {
#address-cells = <1>;
#size-cells = <0>;
device_type = "network";
device-id = <1>;
compatible = "fs_enet";
model = "FCC";
reg = <11300 20 8400 100 11380 30>;
mac-address = [ 00 11 2F 99 43 54 ];
interrupts = <20 2>;
interrupt-parent = <&Cpm_pic>;
phy-handle = <&Phy0>;
rx-clock = <13>;
tx-clock = <12>;
board-control@1,0 {
reg = <1 0 20>;
compatible = "fsl,mpc8272ads-bcsr";
};

ethernet@25000 {
device_type = "network";
device-id = <2>;
compatible = "fs_enet";
model = "FCC";
reg = <11320 20 8500 100 113b0 30>;
mac-address = [ 00 11 2F 99 44 54 ];
interrupts = <21 2>;
interrupt-parent = <&Cpm_pic>;
phy-handle = <&Phy1>;
rx-clock = <17>;
tx-clock = <18>;
PCI_PIC: interrupt-controller@3,0 {
compatible = "fsl,mpc8272ads-pci-pic",
"fsl,pq2ads-pci-pic";
#interrupt-cells = <1>;
interrupt-controller;
reg = <3 0 8>;
interrupt-parent = <&PIC>;
interrupts = <14 8>;
};
};


pci@f0010800 {
device_type = "pci";
reg = <f0010800 10c f00101ac 8 f00101c4 8>;
compatible = "fsl,mpc8272-pci", "fsl,pq2-pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
clock-frequency = <d#66666666>;
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x16 */
b000 0 0 1 &PCI_PIC 0
b000 0 0 2 &PCI_PIC 1
b000 0 0 3 &PCI_PIC 2
b000 0 0 4 &PCI_PIC 3

/* IDSEL 0x17 */
b800 0 0 1 &PCI_PIC 4
b800 0 0 2 &PCI_PIC 5
b800 0 0 3 &PCI_PIC 6
b800 0 0 4 &PCI_PIC 7

/* IDSEL 0x18 */
c000 0 0 1 &PCI_PIC 8
c000 0 0 2 &PCI_PIC 9
c000 0 0 3 &PCI_PIC a
c000 0 0 4 &PCI_PIC b>;

interrupt-parent = <&PIC>;
interrupts = <12 8>;
ranges = <42000000 0 80000000 80000000 0 20000000
02000000 0 a0000000 a0000000 0 20000000
01000000 0 00000000 f6000000 0 02000000>;
};

soc@f0000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "fsl,mpc8272", "fsl,pq2-soc";
ranges = <00000000 f0000000 00053000>;

// Temporary -- will go away once kernel uses ranges for get_immrbase().
reg = <f0000000 00053000>;

cpm@f0000000 {
cpm@119c0 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "cpm";
model = "CPM2";
ranges = <00000000 00000000 20000>;
reg = <0 20000>;
command-proc = <119c0>;
brg-frequency = <17D7840>;
cpm_clk = <BEBC200>;

scc@11a00 {
compatible = "fsl,mpc8272-cpm", "fsl,cpm2";
reg = <119c0 30 0 2000>;
ranges;

brg@119f0 {
compatible = "fsl,mpc8272-brg",
"fsl,cpm2-brg",
"fsl,cpm-brg";
reg = <119f0 10 115f0 10>;
};

serial@11a00 {
device_type = "serial";
compatible = "cpm_uart";
model = "SCC";
device-id = <1>;
compatible = "fsl,mpc8272-scc-uart",
"fsl,cpm2-scc-uart";
reg = <11a00 20 8000 100>;
current-speed = <1c200>;
interrupts = <28 2>;
interrupt-parent = <&Cpm_pic>;
clock-setup = <0 00ffffff>;
rx-clock = <1>;
tx-clock = <1>;
interrupts = <28 8>;
interrupt-parent = <&PIC>;
fsl,cpm-brg = <1>;
fsl,cpm-command = <00800000>;
};

scc@11a60 {
serial@11a60 {
device_type = "serial";
compatible = "cpm_uart";
model = "SCC";
device-id = <4>;
compatible = "fsl,mpc8272-scc-uart",
"fsl,cpm2-scc-uart";
reg = <11a60 20 8300 100>;
current-speed = <1c200>;
interrupts = <2b 2>;
interrupt-parent = <&Cpm_pic>;
clock-setup = <1b ffffff00>;
rx-clock = <4>;
tx-clock = <4>;
interrupts = <2b 8>;
interrupt-parent = <&PIC>;
fsl,cpm-brg = <4>;
fsl,cpm-command = <0ce00000>;
};

mdio@10d40 {
device_type = "mdio";
compatible = "fsl,mpc8272ads-mdio-bitbang",
"fsl,mpc8272-mdio-bitbang",
"fsl,cpm2-mdio-bitbang";
reg = <10d40 14>;
#address-cells = <1>;
#size-cells = <0>;
fsl,mdio-pin = <12>;
fsl,mdc-pin = <13>;

PHY0: ethernet-phy@0 {
interrupt-parent = <&PIC>;
interrupts = <17 8>;
reg = <0>;
device_type = "ethernet-phy";
};

PHY1: ethernet-phy@1 {
interrupt-parent = <&PIC>;
interrupts = <17 8>;
reg = <3>;
device_type = "ethernet-phy";
};
};

ethernet@11300 {
device_type = "network";
compatible = "fsl,mpc8272-fcc-enet",
"fsl,cpm2-fcc-enet";
reg = <11300 20 8400 100 11390 1>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <20 8>;
interrupt-parent = <&PIC>;
phy-handle = <&PHY0>;
linux,network-index = <0>;
fsl,cpm-command = <12000300>;
};

ethernet@11320 {
device_type = "network";
compatible = "fsl,mpc8272-fcc-enet",
"fsl,cpm2-fcc-enet";
reg = <11320 20 8500 100 113b0 1>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <21 8>;
interrupt-parent = <&PIC>;
phy-handle = <&PHY1>;
linux,network-index = <1>;
fsl,cpm-command = <16200300>;
};
};

cpm_pic:interrupt-controller@10c00 {
#address-cells = <0>;
PIC: interrupt-controller@10c00 {
#interrupt-cells = <2>;
interrupt-controller;
reg = <10c00 80>;
device_type = "cpm-pic";
compatible = "CPM2";
};

pci@0500 {
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
compatible = "8272";
device_type = "pci";
reg = <10430 4dc>;
clock-frequency = <3f940aa>;
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x16 */
b000 0 0 1 f8200000 40 8
b000 0 0 2 f8200000 41 8
b000 0 0 3 f8200000 42 8
b000 0 0 4 f8200000 43 8

/* IDSEL 0x17 */
b800 0 0 1 f8200000 43 8
b800 0 0 2 f8200000 40 8
b800 0 0 3 f8200000 41 8
b800 0 0 4 f8200000 42 8

/* IDSEL 0x18 */
c000 0 0 1 f8200000 42 8
c000 0 0 2 f8200000 43 8
c000 0 0 3 f8200000 40 8
c000 0 0 4 f8200000 41 8>;
interrupt-parent = <&Cpm_pic>;
interrupts = <14 8>;
bus-range = <0 0>;
ranges = <02000000 0 80000000 80000000 0 40000000
01000000 0 00000000 f6000000 0 02000000>;
compatible = "fsl,mpc8272-pic", "fsl,cpm2-pic";
};

/* May need to remove if on a part without crypto engine */
crypto@30000 {
device_type = "crypto";
model = "SEC2";
compatible = "talitos";
compatible = "fsl,mpc8272-talitos-sec2",
"fsl,talitos-sec2",
"fsl,talitos",
"talitos";
reg = <30000 10000>;
interrupts = <b 2>;
interrupt-parent = <&Cpm_pic>;
interrupts = <b 8>;
interrupt-parent = <&PIC>;
num-channels = <4>;
channel-fifo-len = <18>;
exec-units-mask = <0000007e>;
/* desc mask is for rev1.x, we need runtime fixup for >=2.x */
descriptor-types-mask = <01010ebf>;
};
};

chosen {
linux,stdout-path = "/soc/cpm/serial@11a00";
};
};
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