---

yaml
---
r: 36047
b: refs/heads/master
c: 36396f3
h: refs/heads/master
i:
  36045: 4bb4d32
  36043: 7551650
  36039: ef37465
  36031: f412790
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: e584ade1a6679bfb417620f15951796bed9805d9
+refs/heads/master: 36396f3c36b04f79438f87a0fccfa76aa3de6af9

trunk/include/asm-mips/hazards.h

@@ -11,7 +11,7 @@
 #define _ASM_HAZARDS_H
 
 
-#ifdef __ASSEMBLER__
+#ifdef __ASSEMBLY__
 #define ASMMACRO(name, code...) .macro name; code; .endm
 #else
 

trunk/include/asm-mips/mach-excite/excite.h

@@ -7,7 +7,7 @@
 
 #define EXCITE_CPU_EXT_CLOCK 100000000
 
-#if !defined(__ASSEMBLER__)
+#if !defined(__ASSEMBLY__)
 void __init excite_kgdb_init(void);
 void excite_procfs_init(void);
 extern unsigned long memsize;

trunk/include/asm-mips/sibyte/sb1250_defs.h

@@ -212,7 +212,7 @@
  * Note: you'll need to define uint32_t and uint64_t in your headers.
  */
 
-#if !defined(__ASSEMBLER__)
+#if !defined(__ASSEMBLY__)
 #define _SB_MAKE64(x) ((uint64_t)(x))
 #define _SB_MAKE32(x) ((uint32_t)(x))
 #else
@@ -251,9 +251,9 @@
  */
 
 
-#if defined(__mips64) && !defined(__ASSEMBLER__)
+#if defined(__mips64) && !defined(__ASSEMBLY__)
 #define SBWRITECSR(csr,val) *((volatile uint64_t *) PHYS_TO_K1(csr)) = (val)
 #define SBREADCSR(csr) (*((volatile uint64_t *) PHYS_TO_K1(csr)))
-#endif /* __ASSEMBLER__ */
+#endif /* __ASSEMBLY__ */
 
 #endif

trunk/include/asm-mips/sibyte/sb1250_scd.h

@@ -149,7 +149,7 @@
  * (For the assembler version, sysrev and dest may be the same register.
  * Also, it clobbers AT.)
  */
-#ifdef __ASSEMBLER__
+#ifdef __ASSEMBLY__
 #define SYS_SOC_TYPE(dest, sysrev)					\
 	.set push ;							\
 	.set reorder ;							\