[SPARC64]: Move over to GENERIC_HARDIRQS.

This is the long overdue conversion of sparc64 over to
the generic IRQ layer.

The kernel image is slightly larger, but the BSS is ~60K
smaller due to the reduced size of struct ino_bucket.

A lot of IRQ implementation details, including ino_bucket,
were moved out of asm-sparc64/irq.h and are now private to
arch/sparc64/kernel/irq.c, and most of the code in irq.c
totally disappeared.

One thing that's different at the moment is IRQ distribution,
we do it at enable_irq() time.  If the cpu mask is ALL then
we round-robin using a global rotating cpu counter, else
we pick the first cpu in the mask to support single cpu
targetting.  This is similar to what powerpc's XICS IRQ
support code does.

This works fine on my UP SB1000, and the SMP build goes
fine and runs on that machine, but lots of testing on
different setups is needed.

Signed-off-by: David S. Miller <davem@davemloft.net>

arch/sparc64/Kconfig

@@ -87,6 +87,10 @@ config SYSVIPC_COMPAT
 	depends on COMPAT && SYSVIPC
 	default y
 
+config GENERIC_HARDIRQS
+	bool
+	default y
+
 menu "General machine setup"
 
 config SMP

arch/sparc64/kernel/devices.c

@@ -157,7 +157,7 @@ unsigned int sun4v_vdev_device_interrupt(unsigned int dev_node)
 		return 0;
 	}
 
-	return sun4v_build_irq(sun4v_vdev_devhandle, irq, 0);
+	return sun4v_build_irq(sun4v_vdev_devhandle, irq);
 }
 
 static const char *cpu_mid_prop(void)

arch/sparc64/kernel/entry.S

@@ -432,7 +432,7 @@ do_ivec:
 	membar		#Sync
 
 	sethi		%hi(ivector_table), %g2
-	sllx		%g3, 5, %g3
+	sllx		%g3, 3, %g3
 	or		%g2, %lo(ivector_table), %g2
 	add		%g2, %g3, %g3