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yaml
---
r: 195052
b: refs/heads/master
c: 8b802a7
h: refs/heads/master
v: v3
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Bruce Allan authored and David S. Miller committed May 13, 2010
1 parent 696d7f8 commit e192571
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Showing 2 changed files with 76 additions and 78 deletions.
2 changes: 1 addition & 1 deletion [refs]
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Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: 757c530407a92fd460d557af59ba86920cf025cb
refs/heads/master: 8b802a7e94c2ed9c6032a88b3ab9860c55cd6378
152 changes: 75 additions & 77 deletions trunk/drivers/net/e1000e/ich8lan.c
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Original file line number Diff line number Diff line change
Expand Up @@ -815,11 +815,16 @@ static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
**/
static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
{
struct e1000_adapter *adapter = hw->adapter;
struct e1000_phy_info *phy = &hw->phy;
u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
s32 ret_val;
s32 ret_val = 0;
u16 word_addr, reg_data, reg_addr, phy_page = 0;

if (!(hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) &&
!(hw->mac.type == e1000_pchlan))
return ret_val;

ret_val = hw->phy.ops.acquire(hw);
if (ret_val)
return ret_val;
Expand All @@ -831,97 +836,90 @@ static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
* Therefore, after each PHY reset, we will load the
* configuration data out of the NVM manually.
*/
if ((hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) ||
(hw->mac.type == e1000_pchlan)) {
struct e1000_adapter *adapter = hw->adapter;

/* Check if SW needs to configure the PHY */
if ((adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
(adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M) ||
(hw->mac.type == e1000_pchlan))
sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
else
sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
if ((adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
(adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M) ||
(hw->mac.type == e1000_pchlan))
sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
else
sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;

data = er32(FEXTNVM);
if (!(data & sw_cfg_mask))
goto out;
data = er32(FEXTNVM);
if (!(data & sw_cfg_mask))
goto out;

/* Wait for basic configuration completes before proceeding */
e1000_lan_init_done_ich8lan(hw);
/* Wait for basic configuration completes before proceeding */
e1000_lan_init_done_ich8lan(hw);

/*
* Make sure HW does not configure LCD from PHY
* extended configuration before SW configuration
*/
data = er32(EXTCNF_CTRL);
if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
goto out;

cnf_size = er32(EXTCNF_SIZE);
cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
if (!cnf_size)
goto out;

cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;

if (!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
(hw->mac.type == e1000_pchlan)) {
/*
* Make sure HW does not configure LCD from PHY
* extended configuration before SW configuration
* HW configures the SMBus address and LEDs when the
* OEM and LCD Write Enable bits are set in the NVM.
* When both NVM bits are cleared, SW will configure
* them instead.
*/
data = er32(EXTCNF_CTRL);
if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
data = er32(STRAP);
data &= E1000_STRAP_SMBUS_ADDRESS_MASK;
reg_data = data >> E1000_STRAP_SMBUS_ADDRESS_SHIFT;
reg_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR,
reg_data);
if (ret_val)
goto out;

cnf_size = er32(EXTCNF_SIZE);
cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
if (!cnf_size)
data = er32(LEDCTL);
ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
(u16)data);
if (ret_val)
goto out;
}

cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;

if (!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
(hw->mac.type == e1000_pchlan)) {
/*
* HW configures the SMBus address and LEDs when the
* OEM and LCD Write Enable bits are set in the NVM.
* When both NVM bits are cleared, SW will configure
* them instead.
*/
data = er32(STRAP);
data &= E1000_STRAP_SMBUS_ADDRESS_MASK;
reg_data = data >> E1000_STRAP_SMBUS_ADDRESS_SHIFT;
reg_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR,
reg_data);
if (ret_val)
goto out;

data = er32(LEDCTL);
ret_val = e1000_write_phy_reg_hv_locked(hw,
HV_LED_CONFIG,
(u16)data);
if (ret_val)
goto out;
}
/* Configure LCD from extended configuration region. */
/* Configure LCD from extended configuration region. */

/* cnf_base_addr is in DWORD */
word_addr = (u16)(cnf_base_addr << 1);
/* cnf_base_addr is in DWORD */
word_addr = (u16)(cnf_base_addr << 1);

for (i = 0; i < cnf_size; i++) {
ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
&reg_data);
if (ret_val)
goto out;
for (i = 0; i < cnf_size; i++) {
ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
&reg_data);
if (ret_val)
goto out;

ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
1, &reg_addr);
if (ret_val)
goto out;
ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
1, &reg_addr);
if (ret_val)
goto out;

/* Save off the PHY page for future writes. */
if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
phy_page = reg_data;
continue;
}
/* Save off the PHY page for future writes. */
if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
phy_page = reg_data;
continue;
}

reg_addr &= PHY_REG_MASK;
reg_addr |= phy_page;
reg_addr &= PHY_REG_MASK;
reg_addr |= phy_page;

ret_val = phy->ops.write_reg_locked(hw,
(u32)reg_addr,
reg_data);
if (ret_val)
goto out;
}
ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
reg_data);
if (ret_val)
goto out;
}

out:
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