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yaml
---
r: 175849
b: refs/heads/master
c: 0c46616
h: refs/heads/master
i:
  175847: 0f8b269
v: v3
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Joakim Tjernlund authored and Benjamin Herrenschmidt committed Dec 9, 2009
1 parent ea24428 commit e1a394b
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Showing 3 changed files with 12 additions and 3 deletions.
2 changes: 1 addition & 1 deletion [refs]
Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: 4a280a413c0c0da03936483384c9e5142966635e
refs/heads/master: 0c4661698c58db2a9efc44f403b893bd4d98f348
5 changes: 3 additions & 2 deletions trunk/arch/powerpc/include/asm/pte-8xx.h
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Expand Up @@ -35,11 +35,12 @@
#define _PAGE_SPECIAL 0x0008 /* SW entry, forced to 0 by the TLB miss */
#define _PAGE_DIRTY 0x0100 /* C: page changed */

/* These 3 software bits must be masked out when the entry is loaded
* into the TLB, 2 SW bits left.
/* These 4 software bits must be masked out when the entry is loaded
* into the TLB, 1 SW bit left(0x0080).
*/
#define _PAGE_GUARDED 0x0010 /* software: guarded access */
#define _PAGE_ACCESSED 0x0020 /* software: page referenced */
#define _PAGE_WRITETHRU 0x0040 /* software: caching is write through */

/* Setting any bits in the nibble with the follow two controls will
* require a TLB exception handler change. It is assumed unused bits
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8 changes: 8 additions & 0 deletions trunk/arch/powerpc/kernel/head_8xx.S
Original file line number Diff line number Diff line change
Expand Up @@ -422,6 +422,10 @@ DataStoreTLBMiss:
* above.
*/
rlwimi r11, r10, 0, 27, 27
/* Insert the WriteThru flag into the TWC from the Linux PTE.
* It is bit 25 in the Linux PTE and bit 30 in the TWC
*/
rlwimi r11, r10, 32-5, 30, 30
DO_8xx_CPU6(0x3b80, r3)
mtspr SPRN_MD_TWC, r11

Expand Down Expand Up @@ -559,6 +563,10 @@ DARFixed:/* Return from dcbx instruction bug workaround, r10 holds value of DAR
* It is bit 27 of both the Linux PTE and the TWC
*/
rlwimi r11, r10, 0, 27, 27
/* Insert the WriteThru flag into the TWC from the Linux PTE.
* It is bit 25 in the Linux PTE and bit 30 in the TWC
*/
rlwimi r11, r10, 32-5, 30, 30
DO_8xx_CPU6(0x3b80, r3)
mtspr SPRN_MD_TWC, r11
mfspr r11, SPRN_MD_TWC /* get the pte address again */
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