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yaml --- r: 123886 b: refs/heads/master c: 26da1bf h: refs/heads/master v: v3
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Ben Dooks
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Dec 15, 2008
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| @@ -1,2 +1,2 @@ | ||
| --- | ||
| refs/heads/master: 4162d7e36334541e9cf5262cb6e1ba4f827eb700 | ||
| refs/heads/master: 26da1bfc567e10ca20cf2ffa97dcdcbd5112275b |
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| /* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-n.h | ||
| * | ||
| * Copyright 2008 Openmoko, Inc. | ||
| * Copyright 2008 Simtec Electronics | ||
| * Ben Dooks <ben@simtec.co.uk> | ||
| * http://armlinux.simtec.co.uk/ | ||
| * | ||
| * GPIO Bank N register and configuration definitions | ||
| * | ||
| * This program is free software; you can redistribute it and/or modify | ||
| * it under the terms of the GNU General Public License version 2 as | ||
| * published by the Free Software Foundation. | ||
| */ | ||
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| #define S3C64XX_GPNCON (S3C64XX_GPN_BASE + 0x00) | ||
| #define S3C64XX_GPNDAT (S3C64XX_GPN_BASE + 0x04) | ||
| #define S3C64XX_GPNPUD (S3C64XX_GPN_BASE + 0x08) | ||
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| #define S3C64XX_GPN_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) | ||
| #define S3C64XX_GPN_INPUT(__gpio) (0x0 << ((__gpio) * 2)) | ||
| #define S3C64XX_GPN_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) | ||
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| #define S3C64XX_GPN0_EINT0 (0x02 << 0) | ||
| #define S3C64XX_GPN0_KP_ROW0 (0x03 << 0) | ||
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| #define S3C64XX_GPN1_EINT1 (0x02 << 2) | ||
| #define S3C64XX_GPN1_KP_ROW1 (0x03 << 2) | ||
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| #define S3C64XX_GPN2_EINT2 (0x02 << 4) | ||
| #define S3C64XX_GPN2_KP_ROW2 (0x03 << 4) | ||
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| #define S3C64XX_GPN3_EINT3 (0x02 << 6) | ||
| #define S3C64XX_GPN3_KP_ROW3 (0x03 << 6) | ||
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| #define S3C64XX_GPN4_EINT4 (0x02 << 8) | ||
| #define S3C64XX_GPN4_KP_ROW4 (0x03 << 8) | ||
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| #define S3C64XX_GPN5_EINT5 (0x02 << 10) | ||
| #define S3C64XX_GPN5_KP_ROW5 (0x03 << 10) | ||
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| #define S3C64XX_GPN6_EINT6 (0x02 << 12) | ||
| #define S3C64XX_GPN6_KP_ROW6 (0x03 << 12) | ||
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| #define S3C64XX_GPN7_EINT7 (0x02 << 14) | ||
| #define S3C64XX_GPN7_KP_ROW7 (0x03 << 14) | ||
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| #define S3C64XX_GPN8_EINT8 (0x02 << 16) | ||
| #define S3C64XX_GPN9_EINT9 (0x02 << 18) | ||
| #define S3C64XX_GPN10_EINT10 (0x02 << 20) | ||
| #define S3C64XX_GPN11_EINT11 (0x02 << 22) | ||
| #define S3C64XX_GPN12_EINT12 (0x02 << 24) | ||
| #define S3C64XX_GPN13_EINT13 (0x02 << 26) | ||
| #define S3C64XX_GPN14_EINT14 (0x02 << 28) | ||
| #define S3C64XX_GPN15_EINT15 (0x02 << 30) |
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| /* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-o.h | ||
| * | ||
| * Copyright 2008 Openmoko, Inc. | ||
| * Copyright 2008 Simtec Electronics | ||
| * Ben Dooks <ben@simtec.co.uk> | ||
| * http://armlinux.simtec.co.uk/ | ||
| * | ||
| * GPIO Bank O register and configuration definitions | ||
| * | ||
| * This program is free software; you can redistribute it and/or modify | ||
| * it under the terms of the GNU General Public License version 2 as | ||
| * published by the Free Software Foundation. | ||
| */ | ||
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| #define S3C64XX_GPOCON (S3C64XX_GPO_BASE + 0x00) | ||
| #define S3C64XX_GPODAT (S3C64XX_GPO_BASE + 0x04) | ||
| #define S3C64XX_GPOPUD (S3C64XX_GPO_BASE + 0x08) | ||
| #define S3C64XX_GPOCONSLP (S3C64XX_GPO_BASE + 0x0c) | ||
| #define S3C64XX_GPOPUDSLP (S3C64XX_GPO_BASE + 0x10) | ||
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| #define S3C64XX_GPO_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) | ||
| #define S3C64XX_GPO_INPUT(__gpio) (0x0 << ((__gpio) * 2)) | ||
| #define S3C64XX_GPO_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) | ||
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| #define S3C64XX_GPO0_MEM0_nCS2 (0x02 << 0) | ||
| #define S3C64XX_GPO0_EINT_G7_0 (0x03 << 0) | ||
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| #define S3C64XX_GPO1_MEM0_nCS3 (0x02 << 2) | ||
| #define S3C64XX_GPO1_EINT_G7_1 (0x03 << 2) | ||
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| #define S3C64XX_GPO2_MEM0_nCS4 (0x02 << 4) | ||
| #define S3C64XX_GPO2_EINT_G7_2 (0x03 << 4) | ||
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| #define S3C64XX_GPO3_MEM0_nCS5 (0x02 << 6) | ||
| #define S3C64XX_GPO3_EINT_G7_3 (0x03 << 6) | ||
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| #define S3C64XX_GPO4_EINT_G7_4 (0x03 << 8) | ||
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| #define S3C64XX_GPO5_EINT_G7_5 (0x03 << 10) | ||
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| #define S3C64XX_GPO6_MEM0_ADDR6 (0x02 << 12) | ||
| #define S3C64XX_GPO6_EINT_G7_6 (0x03 << 12) | ||
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| #define S3C64XX_GPO7_MEM0_ADDR7 (0x02 << 14) | ||
| #define S3C64XX_GPO7_EINT_G7_7 (0x03 << 14) | ||
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| #define S3C64XX_GPO8_MEM0_ADDR8 (0x02 << 16) | ||
| #define S3C64XX_GPO8_EINT_G7_8 (0x03 << 16) | ||
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| #define S3C64XX_GPO9_MEM0_ADDR9 (0x02 << 18) | ||
| #define S3C64XX_GPO9_EINT_G7_9 (0x03 << 18) | ||
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| #define S3C64XX_GPO10_MEM0_ADDR10 (0x02 << 20) | ||
| #define S3C64XX_GPO10_EINT_G7_10 (0x03 << 20) | ||
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| #define S3C64XX_GPO11_MEM0_ADDR11 (0x02 << 22) | ||
| #define S3C64XX_GPO11_EINT_G7_11 (0x03 << 22) | ||
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| #define S3C64XX_GPO12_MEM0_ADDR12 (0x02 << 24) | ||
| #define S3C64XX_GPO12_EINT_G7_12 (0x03 << 24) | ||
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| #define S3C64XX_GPO13_MEM0_ADDR13 (0x02 << 26) | ||
| #define S3C64XX_GPO13_EINT_G7_13 (0x03 << 26) | ||
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| #define S3C64XX_GPO14_MEM0_ADDR14 (0x02 << 28) | ||
| #define S3C64XX_GPO14_EINT_G7_14 (0x03 << 28) | ||
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| #define S3C64XX_GPO15_MEM0_ADDR15 (0x02 << 30) | ||
| #define S3C64XX_GPO15_EINT_G7_15 (0x03 << 30) | ||
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,69 @@ | ||
| /* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-p.h | ||
| * | ||
| * Copyright 2008 Openmoko, Inc. | ||
| * Copyright 2008 Simtec Electronics | ||
| * Ben Dooks <ben@simtec.co.uk> | ||
| * http://armlinux.simtec.co.uk/ | ||
| * | ||
| * GPIO Bank P register and configuration definitions | ||
| * | ||
| * This program is free software; you can redistribute it and/or modify | ||
| * it under the terms of the GNU General Public License version 2 as | ||
| * published by the Free Software Foundation. | ||
| */ | ||
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| #define S3C64XX_GPPCON (S3C64XX_GPP_BASE + 0x00) | ||
| #define S3C64XX_GPPDAT (S3C64XX_GPP_BASE + 0x04) | ||
| #define S3C64XX_GPPPUD (S3C64XX_GPP_BASE + 0x08) | ||
| #define S3C64XX_GPPCONSLP (S3C64XX_GPP_BASE + 0x0c) | ||
| #define S3C64XX_GPPPUDSLP (S3C64XX_GPP_BASE + 0x10) | ||
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| #define S3C64XX_GPP_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) | ||
| #define S3C64XX_GPP_INPUT(__gpio) (0x0 << ((__gpio) * 2)) | ||
| #define S3C64XX_GPP_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) | ||
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| #define S3C64XX_GPP0_MEM0_ADDRV (0x02 << 0) | ||
| #define S3C64XX_GPP0_EINT_G8_0 (0x03 << 0) | ||
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| #define S3C64XX_GPP1_MEM0_SMCLK (0x02 << 2) | ||
| #define S3C64XX_GPP1_EINT_G8_1 (0x03 << 2) | ||
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| #define S3C64XX_GPP2_MEM0_nWAIT (0x02 << 4) | ||
| #define S3C64XX_GPP2_EINT_G8_2 (0x03 << 4) | ||
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| #define S3C64XX_GPP3_MEM0_RDY0_ALE (0x02 << 6) | ||
| #define S3C64XX_GPP3_EINT_G8_3 (0x03 << 6) | ||
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| #define S3C64XX_GPP4_MEM0_RDY1_CLE (0x02 << 8) | ||
| #define S3C64XX_GPP4_EINT_G8_4 (0x03 << 8) | ||
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| #define S3C64XX_GPP5_MEM0_INTsm0_FWE (0x02 << 10) | ||
| #define S3C64XX_GPP5_EINT_G8_5 (0x03 << 10) | ||
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| #define S3C64XX_GPP6_MEM0_(null) (0x02 << 12) | ||
| #define S3C64XX_GPP6_EINT_G8_6 (0x03 << 12) | ||
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| #define S3C64XX_GPP7_MEM0_INTsm1_FRE (0x02 << 14) | ||
| #define S3C64XX_GPP7_EINT_G8_7 (0x03 << 14) | ||
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| #define S3C64XX_GPP8_MEM0_RPn_RnB (0x02 << 16) | ||
| #define S3C64XX_GPP8_EINT_G8_8 (0x03 << 16) | ||
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| #define S3C64XX_GPP9_MEM0_ATA_RESET (0x02 << 18) | ||
| #define S3C64XX_GPP9_EINT_G8_9 (0x03 << 18) | ||
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| #define S3C64XX_GPP10_MEM0_ATA_INPACK (0x02 << 20) | ||
| #define S3C64XX_GPP10_EINT_G8_10 (0x03 << 20) | ||
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| #define S3C64XX_GPP11_MEM0_ATA_REG (0x02 << 22) | ||
| #define S3C64XX_GPP11_EINT_G8_11 (0x03 << 22) | ||
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| #define S3C64XX_GPP12_MEM0_ATA_WE (0x02 << 24) | ||
| #define S3C64XX_GPP12_EINT_G8_12 (0x03 << 24) | ||
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| #define S3C64XX_GPP13_MEM0_ATA_OE (0x02 << 26) | ||
| #define S3C64XX_GPP13_EINT_G8_13 (0x03 << 26) | ||
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| #define S3C64XX_GPP14_MEM0_ATA_CD (0x02 << 28) | ||
| #define S3C64XX_GPP14_EINT_G8_14 (0x03 << 28) | ||
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| Original file line number | Diff line number | Diff line change |
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| @@ -0,0 +1,46 @@ | ||
| /* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-q.h | ||
| * | ||
| * Copyright 2008 Openmoko, Inc. | ||
| * Copyright 2008 Simtec Electronics | ||
| * Ben Dooks <ben@simtec.co.uk> | ||
| * http://armlinux.simtec.co.uk/ | ||
| * | ||
| * GPIO Bank Q register and configuration definitions | ||
| * | ||
| * This program is free software; you can redistribute it and/or modify | ||
| * it under the terms of the GNU General Public License version 2 as | ||
| * published by the Free Software Foundation. | ||
| */ | ||
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| #define S3C64XX_GPQCON (S3C64XX_GPQ_BASE + 0x00) | ||
| #define S3C64XX_GPQDAT (S3C64XX_GPQ_BASE + 0x04) | ||
| #define S3C64XX_GPQPUD (S3C64XX_GPQ_BASE + 0x08) | ||
| #define S3C64XX_GPQCONSLP (S3C64XX_GPQ_BASE + 0x0c) | ||
| #define S3C64XX_GPQPUDSLP (S3C64XX_GPQ_BASE + 0x10) | ||
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| #define S3C64XX_GPQ_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) | ||
| #define S3C64XX_GPQ_INPUT(__gpio) (0x0 << ((__gpio) * 2)) | ||
| #define S3C64XX_GPQ_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) | ||
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| #define S3C64XX_GPQ0_MEM0_ADDR18_RAS (0x02 << 0) | ||
| #define S3C64XX_GPQ0_EINT_G9_0 (0x03 << 0) | ||
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| #define S3C64XX_GPQ1_MEM0_ADDR19_CAS (0x02 << 2) | ||
| #define S3C64XX_GPQ1_EINT_G9_1 (0x03 << 2) | ||
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| #define S3C64XX_GPQ2_EINT_G9_2 (0x03 << 4) | ||
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| #define S3C64XX_GPQ3_EINT_G9_3 (0x03 << 6) | ||
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| #define S3C64XX_GPQ4_EINT_G9_4 (0x03 << 8) | ||
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| #define S3C64XX_GPQ5_EINT_G9_5 (0x03 << 10) | ||
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| #define S3C64XX_GPQ6_EINT_G9_6 (0x03 << 12) | ||
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| #define S3C64XX_GPQ7_MEM0_ADDR17_WENDMC (0x02 << 14) | ||
| #define S3C64XX_GPQ7_EINT_G9_7 (0x03 << 14) | ||
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| #define S3C64XX_GPQ8_MEM0_ADDR16_APDMC (0x02 << 16) | ||
| #define S3C64XX_GPQ8_EINT_G9_8 (0x03 << 16) | ||
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