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yaml
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r: 345240
b: refs/heads/master
c: 7cbfd06
h: refs/heads/master
v: v3
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Paulo Zanoni authored and Daniel Vetter committed Nov 11, 2012
1 parent 48d3411 commit e339092
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Showing 2 changed files with 1 addition and 10 deletions.
2 changes: 1 addition & 1 deletion [refs]
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@@ -1,2 +1,2 @@
---
refs/heads/master: b6b4e185a7d2835fa145bf1a2e3553431cb24a92
refs/heads/master: 7cbfd0653005d6c7a8f00d8ef5573b2976157780
9 changes: 0 additions & 9 deletions trunk/drivers/gpu/drm/i915/intel_display.c
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Expand Up @@ -3181,15 +3181,6 @@ static void lpt_pch_enable(struct drm_crtc *crtc)
/* For PCH output, training FDI link */
dev_priv->display.fdi_link_train(crtc);

/* XXX: pch pll's can be enabled any time before we enable the PCH
* transcoder, and we actually should do this to not upset any PCH
* transcoder that already use the clock when we share it.
*
* Note that enable_pch_pll tries to do the right thing, but get_pch_pll
* unconditionally resets the pll - we need that to have the right LVDS
* enable sequence. */
ironlake_enable_pch_pll(intel_crtc);

lpt_program_iclkip(crtc);

/* set transcoder timing, panel must allow it */
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