viafb: reset correct PLL

Looks like we did reset the PLL of the (whatever) engine instead of the PLL of the secondary display (IGA2, LCDCK). This patch fixes it. Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de> Cc: Joseph Chan <JosephChan@via.com.tw>
git-mirror · Sep 24, 2010 · e3812ce · e3812ce
1 parent b4aaa78
commit e3812ce
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/drivers/video/via/hw.c b/drivers/video/via/hw.c
@@ -1688,8 +1688,8 @@ void viafb_set_vclock(u32 clk, int set_iga)
 	}
 
 	if (set_iga == IGA2) {
-		viafb_write_reg_mask(SR40, VIASR, 0x01, BIT0);
-		viafb_write_reg_mask(SR40, VIASR, 0x00, BIT0);
+		viafb_write_reg_mask(SR40, VIASR, 0x04, BIT2);
+		viafb_write_reg_mask(SR40, VIASR, 0x00, BIT2);
 	}
 
 	/* Fire! */