---

yaml --- r: 331419 b: refs/heads/master c: e1e362d h: refs/heads/master i: 331417: 790bc60 331415: c5d44d2 v: v3
git-mirror · Sep 27, 2012 · e399261 · e399261
1 parent cd67dc0
commit e399261
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Showing 7 changed files with 12 additions and 12 deletions.
diff --git a/[refs] b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 6a3a786d02172b34d0ffba6f80bd1150da51125d
+refs/heads/master: e1e362dc074c2981e7f78d26bf38a4f14be52ecd
diff --git a/trunk/arch/m68k/include/asm/m5206sim.h b/trunk/arch/m68k/include/asm/m5206sim.h
@@ -43,8 +43,8 @@
 #define	MCFSIM_IMR		(MCF_MBAR + 0x36)	/* Interrupt Mask */
 #define	MCFSIM_IPR		(MCF_MBAR + 0x3a)	/* Interrupt Pending */
 
-#define	MCFSIM_RSR		0x40		/* Reset Status reg (r/w) */
-#define	MCFSIM_SYPCR		0x41		/* System Protection reg (r/w)*/
+#define	MCFSIM_RSR		(MCF_MBAR + 0x40)	/* Reset Status */
+#define	MCFSIM_SYPCR		(MCF_MBAR + 0x41)	/* System Protection */
 
 #define	MCFSIM_SWIVR		0x42		/* SW Watchdog intr reg (r/w) */
 #define	MCFSIM_SWSR		0x43		/* SW Watchdog service (r/w) */

diff --git a/trunk/arch/m68k/include/asm/m5249sim.h b/trunk/arch/m68k/include/asm/m5249sim.h
@@ -25,8 +25,8 @@
 /*
  *	Define the 5249 SIM register set addresses.
  */
-#define	MCFSIM_RSR		0x00		/* Reset Status reg (r/w) */
-#define	MCFSIM_SYPCR		0x01		/* System Protection reg (r/w)*/
+#define	MCFSIM_RSR		(MCF_MBAR + 0x00)	/* Reset Status */
+#define	MCFSIM_SYPCR		(MCF_MBAR + 0x01)	/* System Protection */
 #define	MCFSIM_SWIVR		0x02		/* SW Watchdog intr reg (r/w) */
 #define	MCFSIM_SWSR		0x03		/* SW Watchdog service (r/w) */
 #define	MCFSIM_PAR		0x04		/* Pin Assignment reg (r/w) */

diff --git a/trunk/arch/m68k/include/asm/m525xsim.h b/trunk/arch/m68k/include/asm/m525xsim.h
@@ -26,8 +26,8 @@
 /*
  *	Define the 525x SIM register set addresses.
  */
-#define MCFSIM_RSR		0x00		/* Reset Status reg (r/w) */
-#define MCFSIM_SYPCR		0x01		/* System Protection reg (r/w)*/
+#define MCFSIM_RSR		(MCF_MBAR + 0x00)	/* Reset Status */
+#define MCFSIM_SYPCR		(MCF_MBAR + 0x01)	/* System Protection */
 #define MCFSIM_SWIVR		0x02		/* SW Watchdog intr reg (r/w) */
 #define MCFSIM_SWSR		0x03		/* SW Watchdog service (r/w) */
 #define MCFSIM_MPARK		0x0C		/* BUS Master Control Reg*/

diff --git a/trunk/arch/m68k/include/asm/m5307sim.h b/trunk/arch/m68k/include/asm/m5307sim.h
@@ -23,8 +23,8 @@
 /*
  *	Define the 5307 SIM register set addresses.
  */
-#define	MCFSIM_RSR		0x00		/* Reset Status reg (r/w) */
-#define	MCFSIM_SYPCR		0x01		/* System Protection reg (r/w)*/
+#define	MCFSIM_RSR		(MCF_MBAR + 0x00)	/* Reset Status reg */
+#define	MCFSIM_SYPCR		(MCF_MBAR + 0x01)	/* System Protection */
 #define	MCFSIM_SWIVR		0x02		/* SW Watchdog intr reg (r/w) */
 #define	MCFSIM_SWSR		0x03		/* SW Watchdog service (r/w) */
 #define	MCFSIM_PAR		0x04		/* Pin Assignment reg (r/w) */

diff --git a/trunk/arch/m68k/include/asm/m5407sim.h b/trunk/arch/m68k/include/asm/m5407sim.h
@@ -23,8 +23,8 @@
 /*
  *	Define the 5407 SIM register set addresses.
  */
-#define	MCFSIM_RSR		0x00		/* Reset Status reg (r/w) */
-#define	MCFSIM_SYPCR		0x01		/* System Protection reg (r/w)*/
+#define	MCFSIM_RSR		(MCF_MBAR + 0x00)	/* Reset Status */
+#define	MCFSIM_SYPCR		(MCF_MBAR + 0x01)	/* System Protection */
 #define	MCFSIM_SWIVR		0x02		/* SW Watchdog intr reg (r/w) */
 #define	MCFSIM_SWSR		0x03		/* SW Watchdog service (r/w) */
 #define	MCFSIM_PAR		0x04		/* Pin Assignment reg (r/w) */

diff --git a/trunk/arch/m68k/platform/coldfire/reset.c b/trunk/arch/m68k/platform/coldfire/reset.c
@@ -27,7 +27,7 @@ static void mcf_cpu_reset(void)
 {
 	local_irq_disable();
 	/* Set watchdog to soft reset, and enabled */
-	__raw_writeb(0xc0, MCF_MBAR + MCFSIM_SYPCR);
+	__raw_writeb(0xc0, MCFSIM_SYPCR);
 	for (;;)
 		/* wait for watchdog to timeout */;
 }