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ADI AXI-I2S controller | ||
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Required properties: | ||
- compatible : Must be "adi,axi-i2s-1.00.a" | ||
- reg : Must contain I2S core's registers location and length | ||
- clocks : Pairs of phandle and specifier referencing the controller's clocks. | ||
The controller expects two clocks, the clock used for the AXI interface and | ||
the clock used as the sampling rate reference clock sample. | ||
- clock-names : "axi" for the clock to the AXI interface, "ref" for the sample | ||
rate reference clock. | ||
- dmas: Pairs of phandle and specifier for the DMA channels that are used by | ||
the core. The core expects two dma channels, one for transmit and one for | ||
receive. | ||
- dma-names : "tx" for the transmit channel, "rx" for the receive channel. | ||
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For more details on the 'dma', 'dma-names', 'clock' and 'clock-names' properties | ||
please check: | ||
* resource-names.txt | ||
* clock/clock-bindings.txt | ||
* dma/dma.txt | ||
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Example: | ||
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i2s: i2s@0x77600000 { | ||
compatible = "adi,axi-i2s-1.00.a"; | ||
reg = <0x77600000 0x1000>; | ||
clocks = <&clk 15>, <&audio_clock>; | ||
clock-names = "axi", "ref"; | ||
dmas = <&ps7_dma 0>, <&ps7_dma 1>; | ||
dma-names = "tx", "rx"; | ||
}; |
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Documentation/devicetree/bindings/sound/adi,axi-spdif-tx.txt
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ADI AXI-SPDIF controller | ||
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Required properties: | ||
- compatible : Must be "adi,axi-spdif-1.00.a" | ||
- reg : Must contain SPDIF core's registers location and length | ||
- clocks : Pairs of phandle and specifier referencing the controller's clocks. | ||
The controller expects two clocks, the clock used for the AXI interface and | ||
the clock used as the sampling rate reference clock sample. | ||
- clock-names: "axi" for the clock to the AXI interface, "ref" for the sample | ||
rate reference clock. | ||
- dmas: Pairs of phandle and specifier for the DMA channel that is used by | ||
the core. The core expects one dma channel for transmit. | ||
- dma-names : Must be "tx" | ||
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For more details on the 'dma', 'dma-names', 'clock' and 'clock-names' properties | ||
please check: | ||
* resource-names.txt | ||
* clock/clock-bindings.txt | ||
* dma/dma.txt | ||
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Example: | ||
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spdif: spdif@0x77400000 { | ||
compatible = "adi,axi-spdif-tx-1.00.a"; | ||
reg = <0x77600000 0x1000>; | ||
clocks = <&clk 15>, <&audio_clock>; | ||
clock-names = "axi", "ref"; | ||
dmas = <&ps7_dma 0>; | ||
dma-names = "tx"; | ||
}; |
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* Broadcom BCM2835 SoC I2S/PCM module | ||
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Required properties: | ||
- compatible: "brcm,bcm2835-i2s" | ||
- reg: A list of base address and size entries: | ||
* The first entry should cover the PCM registers | ||
* The second entry should cover the PCM clock registers | ||
- dmas: List of DMA controller phandle and DMA request line ordered pairs. | ||
- dma-names: Identifier string for each DMA request line in the dmas property. | ||
These strings correspond 1:1 with the ordered pairs in dmas. | ||
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One of the DMA channels will be responsible for transmission (should be | ||
named "tx") and one for reception (should be named "rx"). | ||
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Example: | ||
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bcm2835_i2s: i2s@7e203000 { | ||
compatible = "brcm,bcm2835-i2s"; | ||
reg = <0x7e203000 0x20>, | ||
<0x7e101098 0x02>; | ||
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dmas = <&dma 2>, | ||
<&dma 3>; | ||
dma-names = "tx", "rx"; | ||
}; |
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CS42L52 audio CODEC | ||
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Required properties: | ||
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- compatible : "cirrus,cs42l52" | ||
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- reg : the I2C address of the device for I2C | ||
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Optional properties: | ||
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- cirrus,reset-gpio : GPIO controller's phandle and the number | ||
of the GPIO used to reset the codec. | ||
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- cirrus,chgfreq-divisor : Values used to set the Charge Pump Frequency. | ||
Allowable values of 0x00 through 0x0F. These are raw values written to the | ||
register, not the actual frequency. The frequency is determined by the following. | ||
Frequency = (64xFs)/(N+2) | ||
N = chgfreq_val | ||
Fs = Sample Rate (variable) | ||
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- cirrus,mica-differential-cfg : boolean, If present, then the MICA input is configured | ||
as a differential input. If not present then the MICA input is configured as | ||
Single-ended input. Single-ended mode allows for MIC1 or MIC2 muxing for input. | ||
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- cirrus,micb-differential-cfg : boolean, If present, then the MICB input is configured | ||
as a differential input. If not present then the MICB input is configured as | ||
Single-ended input. Single-ended mode allows for MIC1 or MIC2 muxing for input. | ||
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- cirrus,micbias-lvl: Set the output voltage level on the MICBIAS Pin | ||
0 = 0.5 x VA | ||
1 = 0.6 x VA | ||
2 = 0.7 x VA | ||
3 = 0.8 x VA | ||
4 = 0.83 x VA | ||
5 = 0.91 x VA | ||
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Example: | ||
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codec: codec@4a { | ||
compatible = "cirrus,cs42l52"; | ||
reg = <0x4a>; | ||
reset-gpio = <&gpio 10 0>; | ||
cirrus,chgfreq-divisor = <0x05>; | ||
cirrus.mica-differential-cfg; | ||
cirrus,micbias-lvl = <5>; | ||
}; |
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Freescale Enhanced Serial Audio Interface (ESAI) Controller | ||
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The Enhanced Serial Audio Interface (ESAI) provides a full-duplex serial port | ||
for serial communication with a variety of serial devices, including industry | ||
standard codecs, Sony/Phillips Digital Interface (S/PDIF) transceivers, and | ||
other DSPs. It has up to six transmitters and four receivers. | ||
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Required properties: | ||
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- compatible : Compatible list, must contain "fsl,imx35-esai". | ||
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- reg : Offset and length of the register set for the device. | ||
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- interrupts : Contains the spdif interrupt. | ||
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- dmas : Generic dma devicetree binding as described in | ||
Documentation/devicetree/bindings/dma/dma.txt. | ||
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- dma-names : Two dmas have to be defined, "tx" and "rx". | ||
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- clocks: Contains an entry for each entry in clock-names. | ||
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- clock-names : Includes the following entries: | ||
"core" The core clock used to access registers | ||
"extal" The esai baud clock for esai controller used to derive | ||
HCK, SCK and FS. | ||
"fsys" The system clock derived from ahb clock used to derive | ||
HCK, SCK and FS. | ||
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- fsl,fifo-depth: The number of elements in the transmit and receive FIFOs. | ||
This number is the maximum allowed value for TFCR[TFWM] or RFCR[RFWM]. | ||
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- fsl,esai-synchronous: This is a boolean property. If present, indicating | ||
that ESAI would work in the synchronous mode, which means all the settings | ||
for Receiving would be duplicated from Transmition related registers. | ||
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Example: | ||
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esai: esai@02024000 { | ||
compatible = "fsl,imx35-esai"; | ||
reg = <0x02024000 0x4000>; | ||
interrupts = <0 51 0x04>; | ||
clocks = <&clks 208>, <&clks 118>, <&clks 208>; | ||
clock-names = "core", "extal", "fsys"; | ||
dmas = <&sdma 23 21 0>, <&sdma 24 21 0>; | ||
dma-names = "rx", "tx"; | ||
fsl,fifo-depth = <128>; | ||
fsl,esai-synchronous; | ||
status = "disabled"; | ||
}; |
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Freescale Synchronous Audio Interface (SAI). | ||
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The SAI is based on I2S module that used communicating with audio codecs, | ||
which provides a synchronous audio interface that supports fullduplex | ||
serial interfaces with frame synchronization such as I2S, AC97, TDM, and | ||
codec/DSP interfaces. | ||
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Required properties: | ||
- compatible: Compatible list, contains "fsl,vf610-sai". | ||
- reg: Offset and length of the register set for the device. | ||
- clocks: Must contain an entry for each entry in clock-names. | ||
- clock-names : Must include the "sai" entry. | ||
- dmas : Generic dma devicetree binding as described in | ||
Documentation/devicetree/bindings/dma/dma.txt. | ||
- dma-names : Two dmas have to be defined, "tx" and "rx". | ||
- pinctrl-names: Must contain a "default" entry. | ||
- pinctrl-NNN: One property must exist for each entry in pinctrl-names. | ||
See ../pinctrl/pinctrl-bindings.txt for details of the property values. | ||
- big-endian-regs: If this property is absent, the little endian mode will | ||
be in use as default, or the big endian mode will be in use for all the | ||
device registers. | ||
- big-endian-data: If this property is absent, the little endian mode will | ||
be in use as default, or the big endian mode will be in use for all the | ||
fifo data. | ||
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Example: | ||
sai2: sai@40031000 { | ||
compatible = "fsl,vf610-sai"; | ||
reg = <0x40031000 0x1000>; | ||
pinctrl-names = "default"; | ||
pinctrl-0 = <&pinctrl_sai2_1>; | ||
clocks = <&clks VF610_CLK_SAI2>; | ||
clock-names = "sai"; | ||
dma-names = "tx", "rx"; | ||
dmas = <&edma0 0 VF610_EDMA_MUXID0_SAI2_TX>, | ||
<&edma0 0 VF610_EDMA_MUXID0_SAI2_RX>; | ||
big-endian-regs; | ||
big-endian-data; | ||
}; |
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Device-Tree bindings for dummy HDMI codec | ||
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Required properties: | ||
- compatible: should be "linux,hdmi-audio". | ||
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CODEC output pins: | ||
* TX | ||
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CODEC input pins: | ||
* RX | ||
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Example node: | ||
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hdmi_audio: hdmi_audio@0 { | ||
compatible = "linux,hdmi-audio"; | ||
status = "okay"; | ||
}; |
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MAX98090 audio CODEC | ||
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This device supports I2C only. | ||
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Required properties: | ||
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- compatible : "maxim,max98090". | ||
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- reg : The I2C address of the device. | ||
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- interrupts : The CODEC's interrupt output. | ||
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Pins on the device (for linking into audio routes): | ||
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* MIC1 | ||
* MIC2 | ||
* DMICL | ||
* DMICR | ||
* IN1 | ||
* IN2 | ||
* IN3 | ||
* IN4 | ||
* IN5 | ||
* IN6 | ||
* IN12 | ||
* IN34 | ||
* IN56 | ||
* HPL | ||
* HPR | ||
* SPKL | ||
* SPKR | ||
* RCVL | ||
* RCVR | ||
* MICBIAS | ||
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Example: | ||
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audio-codec@10 { | ||
compatible = "maxim,max98090"; | ||
reg = <0x10>; | ||
interrupt-parent = <&gpio>; | ||
interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>; | ||
}; |
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Documentation/devicetree/bindings/sound/nvidia,tegra-audio-max98090.txt
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NVIDIA Tegra audio complex, with MAX98090 CODEC | ||
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Required properties: | ||
- compatible : "nvidia,tegra-audio-max98090" | ||
- clocks : Must contain an entry for each entry in clock-names. | ||
See ../clocks/clock-bindings.txt for details. | ||
- clock-names : Must include the following entries: | ||
- pll_a | ||
- pll_a_out0 | ||
- mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk) | ||
- nvidia,model : The user-visible name of this sound complex. | ||
- nvidia,audio-routing : A list of the connections between audio components. | ||
Each entry is a pair of strings, the first being the connection's sink, | ||
the second being the connection's source. Valid names for sources and | ||
sinks are the MAX98090's pins (as documented in its binding), and the jacks | ||
on the board: | ||
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* Headphones | ||
* Speakers | ||
* Mic Jack | ||
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- nvidia,i2s-controller : The phandle of the Tegra I2S controller that's | ||
connected to the CODEC. | ||
- nvidia,audio-codec : The phandle of the MAX98090 audio codec. | ||
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Optional properties: | ||
- nvidia,hp-det-gpios : The GPIO that detect headphones are plugged in | ||
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Example: | ||
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sound { | ||
compatible = "nvidia,tegra-audio-max98090-venice2", | ||
"nvidia,tegra-audio-max98090"; | ||
nvidia,model = "NVIDIA Tegra Venice2"; | ||
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nvidia,audio-routing = | ||
"Headphones", "HPR", | ||
"Headphones", "HPL", | ||
"Speakers", "SPKR", | ||
"Speakers", "SPKL", | ||
"Mic Jack", "MICBIAS", | ||
"IN34", "Mic Jack"; | ||
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nvidia,i2s-controller = <&tegra_i2s1>; | ||
nvidia,audio-codec = <&acodec>; | ||
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clocks = <&tegra_car TEGRA124_CLK_PLL_A>, | ||
<&tegra_car TEGRA124_CLK_PLL_A_OUT0>, | ||
<&tegra_car TEGRA124_CLK_EXTERN1>; | ||
clock-names = "pll_a", "pll_a_out0", "mclk"; | ||
}; |
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