---

yaml
---
r: 311076
b: refs/heads/master
c: 9d88fc0
h: refs/heads/master
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 02edf6abe01610a5fb379df442de3c837ad99467
+refs/heads/master: 9d88fc0b3503e80ab1a5c9fb3b3f074302f44b33

trunk/Documentation/hwmon/coretemp

@@ -6,9 +6,7 @@ Supported chips:
     Prefix: 'coretemp'
     CPUID: family 0x6, models 0xe (Pentium M DC), 0xf (Core 2 DC 65nm),
                               0x16 (Core 2 SC 65nm), 0x17 (Penryn 45nm),
-                              0x1a (Nehalem), 0x1c (Atom), 0x1e (Lynnfield),
-                              0x26 (Tunnel Creek Atom), 0x27 (Medfield Atom),
-                              0x36 (Cedar Trail Atom)
+                              0x1a (Nehalem), 0x1c (Atom), 0x1e (Lynnfield)
     Datasheet: Intel 64 and IA-32 Architectures Software Developer's Manual
                Volume 3A: System Programming Guide
                http://softwarecommunity.intel.com/Wiki/Mobility/720.htm
@@ -54,17 +52,6 @@ Some information comes from ark.intel.com
 
 Process		Processor					TjMax(C)
 
-22nm		Core i5/i7 Processors
-		i7 3920XM, 3820QM, 3720QM, 3667U, 3520M		105
-		i5 3427U, 3360M/3320M				105
-		i7 3770/3770K					105
-		i5 3570/3570K, 3550, 3470/3450			105
-		i7 3770S					103
-		i5 3570S/3550S, 3475S/3470S/3450S		103
-		i7 3770T					94
-		i5 3570T					94
-		i5 3470T					91
-
 32nm		Core i3/i5/i7 Processors
 		i7 660UM/640/620, 640LM/620, 620M, 610E		105
 		i5 540UM/520/430, 540M/520/450/430		105
@@ -78,11 +65,6 @@ Process		Processor					TjMax(C)
 		U3400						105
 		P4505/P4500 					90
 
-32nm		Atom Processors
-		Z2460						90
-		D2700/2550/2500					100
-		N2850/2800/2650/2600				100
-
 45nm		Xeon Processors 5400 Quad-Core
 		X5492, X5482, X5472, X5470, X5460, X5450	85
 		E5472, E5462, E5450/40/30/20/10/05		85
@@ -103,8 +85,6 @@ Process		Processor					TjMax(C)
 		N475/470/455/450				100
 		N280/270					90
 		330/230						125
-		E680/660/640/620				90
-		E680T/660T/640T/620T				110
 
 45nm		Core2 Processors
 		Solo ULV SU3500/3300				100

trunk/Documentation/kernel-parameters.txt

@@ -2543,15 +2543,6 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
 
 	sched_debug	[KNL] Enables verbose scheduler debug messages.
 
-	skew_tick=	[KNL] Offset the periodic timer tick per cpu to mitigate
-			xtime_lock contention on larger systems, and/or RCU lock
-			contention on all systems with CONFIG_MAXSMP set.
-			Format: { "0" | "1" }
-			0 -- disable. (may be 1 via CONFIG_CMDLINE="skew_tick=1"
-			1 -- enable.
-			Note: increases power consumption, thus should only be
-			enabled if running jitter sensitive (HPC/RT) workloads.
-
 	security=	[SECURITY] Choose a security module to enable at boot.
 			If this boot parameter is not specified, only the first
 			security module asking for security registration will be

trunk/Documentation/networking/stmmac.txt

@@ -10,8 +10,8 @@ Currently this network device driver is for all STM embedded MAC/GMAC
 (i.e. 7xxx/5xxx SoCs), SPEAr (arm), Loongson1B (mips) and XLINX XC2V3000
 FF1152AMT0221 D1215994A VIRTEX FPGA board.
 
-DWC Ether MAC 10/100/1000 Universal version 3.60a (and older) and DWC Ether
-MAC 10/100 Universal version 4.0 have been used for developing this driver.
+DWC Ether MAC 10/100/1000 Universal version 3.60a (and older) and DWC Ether MAC 10/100
+Universal version 4.0 have been used for developing this driver.
 
 This driver supports both the platform bus and PCI.
 
@@ -54,27 +54,27 @@ net_device structure enabling the scatter/gather feature.
 When one or more packets are received, an interrupt happens. The interrupts
 are not queued so the driver has to scan all the descriptors in the ring during
 the receive process.
-This is based on NAPI so the interrupt handler signals only if there is work
-to be done, and it exits.
+This is based on NAPI so the interrupt handler signals only if there is work to be
+done, and it exits.
 Then the poll method will be scheduled at some future point.
 The incoming packets are stored, by the DMA, in a list of pre-allocated socket
 buffers in order to avoid the memcpy (Zero-copy).
 
 4.3) Timer-Driver Interrupt
-Instead of having the device that asynchronously notifies the frame receptions,
-the driver configures a timer to generate an interrupt at regular intervals.
-Based on the granularity of the timer, the frames that are received by the
-device will experience different levels of latency. Some NICs have dedicated
-timer device to perform this task. STMMAC can use either the RTC device or the
-TMU channel 2  on STLinux platforms.
+Instead of having the device that asynchronously notifies the frame receptions, the
+driver configures a timer to generate an interrupt at regular intervals.
+Based on the granularity of the timer, the frames that are received by the device
+will experience different levels of latency. Some NICs have dedicated timer
+device to perform this task. STMMAC can use either the RTC device or the TMU
+channel 2  on STLinux platforms.
 The timers frequency can be passed to the driver as parameter; when change it,
 take care of both hardware capability and network stability/performance impact.
-Several performance tests on STM platforms showed this optimisation allows to
-spare the CPU while having the maximum throughput.
+Several performance tests on STM platforms showed this optimisation allows to spare
+the CPU while having the maximum throughput.
 
 4.4) WOL
-Wake up on Lan feature through Magic and Unicast frames are supported for the
-GMAC core.
+Wake up on Lan feature through Magic and Unicast frames are supported for the GMAC
+core.
 
 4.5) DMA descriptors
 Driver handles both normal and enhanced descriptors. The latter has been only
@@ -106,8 +106,7 @@ Several driver's information can be passed through the platform
 These are included in the include/linux/stmmac.h header file
 and detailed below as well:
 
-struct plat_stmmacenet_data {
-	char *phy_bus_name;
+ struct plat_stmmacenet_data {
 	int bus_id;
 	int phy_addr;
 	int interface;
@@ -125,24 +124,19 @@ struct plat_stmmacenet_data {
 	void (*bus_setup)(void __iomem *ioaddr);
 	int (*init)(struct platform_device *pdev);
 	void (*exit)(struct platform_device *pdev);
-	void *custom_cfg;
-	void *custom_data;
 	void *bsp_priv;
  };
 
 Where:
- o phy_bus_name: phy bus name to attach to the stmmac.
  o bus_id: bus identifier.
  o phy_addr: the physical address can be passed from the platform.
 	    If it is set to -1 the driver will automatically
 	    detect it at run-time by probing all the 32 addresses.
  o interface: PHY device's interface.
  o mdio_bus_data: specific platform fields for the MDIO bus.
- o dma_cfg: internal DMA parameters
-   o pbl: the Programmable Burst Length is maximum number of beats to
+ o pbl: the Programmable Burst Length is maximum number of beats to
        be transferred in one DMA transaction.
        GMAC also enables the 4xPBL by default.
-   o fixed_burst/mixed_burst/burst_len
  o clk_csr: fixed CSR Clock range selection.
  o has_gmac: uses the GMAC core.
  o enh_desc: if sets the MAC will use the enhanced descriptor structure.
@@ -166,9 +160,8 @@ Where:
 	     this is sometime necessary on some platforms (e.g. ST boxes)
 	     where the HW needs to have set some PIO lines or system cfg
 	     registers.
- o custom_cfg/custom_data: this is a custom configuration that can be passed
-			   while initialising the resources.
- o bsp_priv: another private poiter.
+ o custom_cfg: this is a custom configuration that can be passed while
+	      initialising the resources.
 
 For MDIO bus The we have:
 
@@ -187,6 +180,7 @@ Where:
  o irqs: list of IRQs, one per PHY.
  o probed_phy_irq: if irqs is NULL, use this for probed PHY.
 
+
 For DMA engine we have the following internal fields that should be
 tuned according to the HW capabilities.