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powerpc/fsl: Add fsl,portid-mapping to corenet1-cf chips
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Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Diana Craciun <diana.craciun@freescale.com>
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Scott Wood committed May 22, 2014
1 parent 8cb5978 commit e83eb02
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Showing 10 changed files with 27 additions and 0 deletions.
1 change: 1 addition & 0 deletions arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
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Expand Up @@ -262,6 +262,7 @@
interrupts = <
24 2 0 0
16 2 1 30>;
fsl,portid-mapping = <0x0f000000>;

pamu0: pamu@0 {
reg = <0 0x1000>;
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4 changes: 4 additions & 0 deletions arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
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Expand Up @@ -83,6 +83,7 @@
reg = <0>;
clocks = <&mux0>;
next-level-cache = <&L2_0>;
fsl,portid-mapping = <0x80000000>;
L2_0: l2-cache {
next-level-cache = <&cpc>;
};
Expand All @@ -92,6 +93,7 @@
reg = <1>;
clocks = <&mux1>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x40000000>;
L2_1: l2-cache {
next-level-cache = <&cpc>;
};
Expand All @@ -101,6 +103,7 @@
reg = <2>;
clocks = <&mux2>;
next-level-cache = <&L2_2>;
fsl,portid-mapping = <0x20000000>;
L2_2: l2-cache {
next-level-cache = <&cpc>;
};
Expand All @@ -110,6 +113,7 @@
reg = <3>;
clocks = <&mux3>;
next-level-cache = <&L2_3>;
fsl,portid-mapping = <0x10000000>;
L2_3: l2-cache {
next-level-cache = <&cpc>;
};
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1 change: 1 addition & 0 deletions arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
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Expand Up @@ -289,6 +289,7 @@
interrupts = <
24 2 0 0
16 2 1 30>;
fsl,portid-mapping = <0x0f000000>;

pamu0: pamu@0 {
reg = <0 0x1000>;
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4 changes: 4 additions & 0 deletions arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
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Expand Up @@ -84,6 +84,7 @@
reg = <0>;
clocks = <&mux0>;
next-level-cache = <&L2_0>;
fsl,portid-mapping = <0x80000000>;
L2_0: l2-cache {
next-level-cache = <&cpc>;
};
Expand All @@ -93,6 +94,7 @@
reg = <1>;
clocks = <&mux1>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x40000000>;
L2_1: l2-cache {
next-level-cache = <&cpc>;
};
Expand All @@ -102,6 +104,7 @@
reg = <2>;
clocks = <&mux2>;
next-level-cache = <&L2_2>;
fsl,portid-mapping = <0x20000000>;
L2_2: l2-cache {
next-level-cache = <&cpc>;
};
Expand All @@ -111,6 +114,7 @@
reg = <3>;
clocks = <&mux3>;
next-level-cache = <&L2_3>;
fsl,portid-mapping = <0x10000000>;
L2_3: l2-cache {
next-level-cache = <&cpc>;
};
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1 change: 1 addition & 0 deletions arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
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Expand Up @@ -297,6 +297,7 @@
interrupts = <
24 2 0 0
16 2 1 30>;
fsl,portid-mapping = <0x00f80000>;

pamu0: pamu@0 {
reg = <0 0x1000>;
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8 changes: 8 additions & 0 deletions arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
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Expand Up @@ -83,6 +83,7 @@
reg = <0>;
clocks = <&mux0>;
next-level-cache = <&L2_0>;
fsl,portid-mapping = <0x80000000>;
L2_0: l2-cache {
next-level-cache = <&cpc>;
};
Expand All @@ -92,6 +93,7 @@
reg = <1>;
clocks = <&mux1>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x40000000>;
L2_1: l2-cache {
next-level-cache = <&cpc>;
};
Expand All @@ -101,6 +103,7 @@
reg = <2>;
clocks = <&mux2>;
next-level-cache = <&L2_2>;
fsl,portid-mapping = <0x20000000>;
L2_2: l2-cache {
next-level-cache = <&cpc>;
};
Expand All @@ -110,6 +113,7 @@
reg = <3>;
clocks = <&mux3>;
next-level-cache = <&L2_3>;
fsl,portid-mapping = <0x10000000>;
L2_3: l2-cache {
next-level-cache = <&cpc>;
};
Expand All @@ -119,6 +123,7 @@
reg = <4>;
clocks = <&mux4>;
next-level-cache = <&L2_4>;
fsl,portid-mapping = <0x08000000>;
L2_4: l2-cache {
next-level-cache = <&cpc>;
};
Expand All @@ -128,6 +133,7 @@
reg = <5>;
clocks = <&mux5>;
next-level-cache = <&L2_5>;
fsl,portid-mapping = <0x04000000>;
L2_5: l2-cache {
next-level-cache = <&cpc>;
};
Expand All @@ -137,6 +143,7 @@
reg = <6>;
clocks = <&mux6>;
next-level-cache = <&L2_6>;
fsl,portid-mapping = <0x02000000>;
L2_6: l2-cache {
next-level-cache = <&cpc>;
};
Expand All @@ -146,6 +153,7 @@
reg = <7>;
clocks = <&mux7>;
next-level-cache = <&L2_7>;
fsl,portid-mapping = <0x01000000>;
L2_7: l2-cache {
next-level-cache = <&cpc>;
};
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1 change: 1 addition & 0 deletions arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
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Expand Up @@ -294,6 +294,7 @@
interrupts = <
24 2 0 0
16 2 1 30>;
fsl,portid-mapping = <0x3c000000>;

pamu0: pamu@0 {
reg = <0 0x1000>;
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2 changes: 2 additions & 0 deletions arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
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Expand Up @@ -90,6 +90,7 @@
reg = <0>;
clocks = <&mux0>;
next-level-cache = <&L2_0>;
fsl,portid-mapping = <0x80000000>;
L2_0: l2-cache {
next-level-cache = <&cpc>;
};
Expand All @@ -99,6 +100,7 @@
reg = <1>;
clocks = <&mux1>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x40000000>;
L2_1: l2-cache {
next-level-cache = <&cpc>;
};
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1 change: 1 addition & 0 deletions arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
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Expand Up @@ -248,6 +248,7 @@
#size-cells = <1>;
interrupts = <24 2 0 0
16 2 1 30>;
fsl,portid-mapping = <0x0f800000>;

pamu0: pamu@0 {
reg = <0 0x1000>;
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4 changes: 4 additions & 0 deletions arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
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Expand Up @@ -83,6 +83,7 @@
reg = <0>;
clocks = <&mux0>;
next-level-cache = <&L2_0>;
fsl,portid-mapping = <0x80000000>;
L2_0: l2-cache {
next-level-cache = <&cpc>;
};
Expand All @@ -92,6 +93,7 @@
reg = <1>;
clocks = <&mux1>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x40000000>;
L2_1: l2-cache {
next-level-cache = <&cpc>;
};
Expand All @@ -101,6 +103,7 @@
reg = <2>;
clocks = <&mux2>;
next-level-cache = <&L2_2>;
fsl,portid-mapping = <0x20000000>;
L2_2: l2-cache {
next-level-cache = <&cpc>;
};
Expand All @@ -110,6 +113,7 @@
reg = <3>;
clocks = <&mux3>;
next-level-cache = <&L2_3>;
fsl,portid-mapping = <0x10000000>;
L2_3: l2-cache {
next-level-cache = <&cpc>;
};
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