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yaml
---
r: 303389
b: refs/heads/master
c: 5a68a73
h: refs/heads/master
i:
  303387: 2a93baa
v: v3
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Santosh Shilimkar authored and Paul Walmsley committed May 8, 2012
1 parent 1e1bedc commit e8aae8a
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Showing 10 changed files with 30 additions and 38 deletions.
2 changes: 1 addition & 1 deletion [refs]
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@@ -1,2 +1,2 @@
---
refs/heads/master: 8f97437eb54f32bb8678904c2f827a853a3d076c
refs/heads/master: 5a68a736581290d10e2ebaf2e5baa8e21eed6dd5
2 changes: 1 addition & 1 deletion trunk/arch/arm/mach-omap2/clock.c
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Expand Up @@ -439,7 +439,7 @@ void omap2_clk_disable_unused(struct clk *clk)
clk->ops->disable(clk);
}
if (clk->clkdm != NULL)
pwrdm_clkdm_state_switch(clk->clkdm);
pwrdm_state_switch(clk->clkdm->pwrdm.ptr);
}
#endif

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3 changes: 1 addition & 2 deletions trunk/arch/arm/mach-omap2/clock3xxx_data.c
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@@ -1,7 +1,7 @@
/*
* OMAP3 clock data
*
* Copyright (C) 2007-2010, 2012 Texas Instruments, Inc.
* Copyright (C) 2007-2010 Texas Instruments, Inc.
* Copyright (C) 2007-2011 Nokia Corporation
*
* Written by Paul Walmsley
Expand Down Expand Up @@ -1640,7 +1640,6 @@ static struct clk hdq_fck = {
.name = "hdq_fck",
.ops = &clkops_omap2_dflt_wait,
.parent = &core_12m_fck,
.clkdm_name = "core_l4_clkdm",
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_HDQ_SHIFT,
.recalc = &followparent_recalc,
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11 changes: 11 additions & 0 deletions trunk/arch/arm/mach-omap2/clock44xx_data.c
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Expand Up @@ -3355,6 +3355,17 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X),
CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X),
CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X),
CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X),
CLK(NULL, "gpt2_ick", &dummy_ck, CK_443X),
CLK(NULL, "gpt3_ick", &dummy_ck, CK_443X),
CLK(NULL, "gpt4_ick", &dummy_ck, CK_443X),
CLK(NULL, "gpt5_ick", &dummy_ck, CK_443X),
CLK(NULL, "gpt6_ick", &dummy_ck, CK_443X),
CLK(NULL, "gpt7_ick", &dummy_ck, CK_443X),
CLK(NULL, "gpt8_ick", &dummy_ck, CK_443X),
CLK(NULL, "gpt9_ick", &dummy_ck, CK_443X),
CLK(NULL, "gpt10_ick", &dummy_ck, CK_443X),
CLK(NULL, "gpt11_ick", &dummy_ck, CK_443X),
CLK("omap_i2c.1", "ick", &dummy_ck, CK_443X),
CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X),
CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X),
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7 changes: 3 additions & 4 deletions trunk/arch/arm/mach-omap2/clockdomain.c
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Expand Up @@ -840,7 +840,7 @@ void clkdm_allow_idle(struct clockdomain *clkdm)
spin_lock_irqsave(&clkdm->lock, flags);
clkdm->_flags |= _CLKDM_FLAG_HWSUP_ENABLED;
arch_clkdm->clkdm_allow_idle(clkdm);
pwrdm_clkdm_state_switch(clkdm);
pwrdm_state_switch(clkdm->pwrdm.ptr);
spin_unlock_irqrestore(&clkdm->lock, flags);
}

Expand Down Expand Up @@ -924,8 +924,7 @@ static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm)

spin_lock_irqsave(&clkdm->lock, flags);
arch_clkdm->clkdm_clk_enable(clkdm);
pwrdm_wait_transition(clkdm->pwrdm.ptr);
pwrdm_clkdm_state_switch(clkdm);
pwrdm_state_switch(clkdm->pwrdm.ptr);
spin_unlock_irqrestore(&clkdm->lock, flags);

pr_debug("clockdomain: clkdm %s: enabled\n", clkdm->name);
Expand All @@ -950,7 +949,7 @@ static int _clkdm_clk_hwmod_disable(struct clockdomain *clkdm)

spin_lock_irqsave(&clkdm->lock, flags);
arch_clkdm->clkdm_clk_disable(clkdm);
pwrdm_clkdm_state_switch(clkdm);
pwrdm_state_switch(clkdm->pwrdm.ptr);
spin_unlock_irqrestore(&clkdm->lock, flags);

pr_debug("clockdomain: clkdm %s: disabled\n", clkdm->name);
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23 changes: 5 additions & 18 deletions trunk/arch/arm/mach-omap2/dpll3xxx.c
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Expand Up @@ -142,8 +142,7 @@ static int _omap3_noncore_dpll_lock(struct clk *clk)

ai = omap3_dpll_autoidle_read(clk);

if (ai)
omap3_dpll_deny_idle(clk);
omap3_dpll_deny_idle(clk);

_omap3_dpll_write_clken(clk, DPLL_LOCKED);

Expand Down Expand Up @@ -187,6 +186,8 @@ static int _omap3_noncore_dpll_bypass(struct clk *clk)

if (ai)
omap3_dpll_allow_idle(clk);
else
omap3_dpll_deny_idle(clk);

return r;
}
Expand Down Expand Up @@ -215,6 +216,8 @@ static int _omap3_noncore_dpll_stop(struct clk *clk)

if (ai)
omap3_dpll_allow_idle(clk);
else
omap3_dpll_deny_idle(clk);

return 0;
}
Expand Down Expand Up @@ -516,9 +519,6 @@ u32 omap3_dpll_autoidle_read(struct clk *clk)

dd = clk->dpll_data;

if (!dd->autoidle_reg)
return -EINVAL;

v = __raw_readl(dd->autoidle_reg);
v &= dd->autoidle_mask;
v >>= __ffs(dd->autoidle_mask);
Expand All @@ -545,12 +545,6 @@ void omap3_dpll_allow_idle(struct clk *clk)

dd = clk->dpll_data;

if (!dd->autoidle_reg) {
pr_debug("clock: DPLL %s: autoidle not supported\n",
clk->name);
return;
}

/*
* REVISIT: CORE DPLL can optionally enter low-power bypass
* by writing 0x5 instead of 0x1. Add some mechanism to
Expand All @@ -560,7 +554,6 @@ void omap3_dpll_allow_idle(struct clk *clk)
v &= ~dd->autoidle_mask;
v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
__raw_writel(v, dd->autoidle_reg);

}

/**
Expand All @@ -579,12 +572,6 @@ void omap3_dpll_deny_idle(struct clk *clk)

dd = clk->dpll_data;

if (!dd->autoidle_reg) {
pr_debug("clock: DPLL %s: autoidle not supported\n",
clk->name);
return;
}

v = __raw_readl(dd->autoidle_reg);
v &= ~dd->autoidle_mask;
v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
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10 changes: 0 additions & 10 deletions trunk/arch/arm/mach-omap2/powerdomain.c
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Expand Up @@ -981,16 +981,6 @@ int pwrdm_state_switch(struct powerdomain *pwrdm)
return ret;
}

int pwrdm_clkdm_state_switch(struct clockdomain *clkdm)
{
if (clkdm != NULL && clkdm->pwrdm.ptr != NULL) {
pwrdm_wait_transition(clkdm->pwrdm.ptr);
return pwrdm_state_switch(clkdm->pwrdm.ptr);
}

return -EINVAL;
}

int pwrdm_pre_transition(void)
{
pwrdm_for_each(_pwrdm_pre_transition_cb, NULL);
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1 change: 0 additions & 1 deletion trunk/arch/arm/mach-omap2/powerdomain.h
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Expand Up @@ -213,7 +213,6 @@ bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
int pwrdm_wait_transition(struct powerdomain *pwrdm);

int pwrdm_state_switch(struct powerdomain *pwrdm);
int pwrdm_clkdm_state_switch(struct clockdomain *clkdm);
int pwrdm_pre_transition(void);
int pwrdm_post_transition(void);
int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm);
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7 changes: 7 additions & 0 deletions trunk/arch/arm/mach-omap2/timer.c
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Expand Up @@ -178,6 +178,13 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
if (IS_ERR(timer->fclk))
return -ENODEV;

sprintf(name, "gpt%d_ick", gptimer_id);
timer->iclk = clk_get(NULL, name);
if (IS_ERR(timer->iclk)) {
clk_put(timer->fclk);
return -ENODEV;
}

omap_hwmod_enable(oh);

sys_timer_reserved |= (1 << (gptimer_id - 1));
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2 changes: 1 addition & 1 deletion trunk/arch/arm/plat-omap/include/plat/dmtimer.h
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Expand Up @@ -259,7 +259,7 @@ struct omap_dm_timer {
unsigned long phys_base;
int id;
int irq;
struct clk *fclk;
struct clk *iclk, *fclk;

void __iomem *io_base;
void __iomem *sys_stat; /* TISTAT timer status */
Expand Down

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