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yaml --- r: 258216 b: refs/heads/master c: e73c34c h: refs/heads/master v: v3
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Mark Rutland
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Russell King
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Jun 29, 2011
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refs/heads/master: ae0c3751ab08d3fe039d48935e9ad2c46711b23b | ||
refs/heads/master: e73c34c3d522a60d9f7b38a7683076362bad98f5 |
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* ARM Performance Monitor Units | ||
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ARM cores often have a PMU for counting cpu and cache events like cache misses | ||
and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU | ||
representation in the device tree should be done as under:- | ||
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Required properties: | ||
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- compatible : should be one of | ||
"arm,cortex-a9-pmu" | ||
"arm,cortex-a8-pmu" | ||
"arm,arm1176-pmu" | ||
"arm,arm1136-pmu" | ||
- interrupts : 1 combined interrupt or 1 per core. | ||
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Example: | ||
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pmu { | ||
compatible = "arm,cortex-a9-pmu"; | ||
interrupts = <100 101>; | ||
}; |
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