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yaml
---
r: 162358
b: refs/heads/master
c: 79de99e
h: refs/heads/master
v: v3
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Alan Cox authored and Greg Kroah-Hartman committed Sep 15, 2009
1 parent fdc0e04 commit ea4e889
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Showing 5 changed files with 59 additions and 140 deletions.
2 changes: 1 addition & 1 deletion [refs]
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Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: f5e3980f9b28b703bc009af9dfa33ae2236503da
refs/heads/master: 79de99e864fb731392bec78f251ce0310fed5d9a
20 changes: 15 additions & 5 deletions trunk/drivers/staging/sep/sep_dev.h
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Original file line number Diff line number Diff line change
Expand Up @@ -60,7 +60,7 @@ struct sep_device {
unsigned long rar_region_addr;

/* start address of the access to the SEP registers from driver */
unsigned long reg_base_address;
void __iomem *reg_base_address;
/* transaction counter that coordinates the transactions between SEP and HOST */
unsigned long host_to_sep_send_counter;
/* counter for the messages from sep */
Expand Down Expand Up @@ -103,17 +103,27 @@ struct sep_device {

extern struct sep_device *sep_dev;

extern inline void sep_write_reg(struct sep_device *dev, int reg, u32 value)
static inline void sep_write_reg(struct sep_device *dev, int reg, u32 value)
{
void __iomem *addr = dev->reg_base_address + reg;
writel(value, reg);
writel(value, addr);
}

extern inline u32 sep_read_reg(struct sep_device *dev, int reg)
static inline u32 sep_read_reg(struct sep_device *dev, int reg)
{
void __iomem *addr = dev->reg_base_address + reg;
return readl(reg);
return readl(addr);
}

/* wait for SRAM write complete(indirect write */
static inline void sep_wait_sram_write(struct sep_device *dev)
{
u32 reg_val;
do
reg_val = sep_read_reg(dev, HW_SRAM_DATA_READY_REG_ADDR);
while(!(reg_val & 1));
}


#endif

56 changes: 0 additions & 56 deletions trunk/drivers/staging/sep/sep_driver_config.h
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Original file line number Diff line number Diff line change
Expand Up @@ -244,62 +244,6 @@ do { \
printk(KERN_WARNING info, param1, param2, param3, param4); \
} while (0)

#if 0
/* write register macro with option for debug print */
#define SEP_WRITE_REGISTER(address, value) \
do { \
if (sepDebug & SEP_DEBUG_LEVEL_REGISTERS) \
printk(KERN_WARNING "Write Register: address %lu value %lu\n", \
(unsigned long)(address), (unsigned long)(value)); \
writel((value), (void *)(address)); \
} while (0)

/* read register macro with option for debug print */
#define SEP_READ_REGISTER(address , value) \
do { \
(value) = readl((void *)(address)); \
if (sepDebug & SEP_DEBUG_LEVEL_REGISTERS) \
printk(KERN_WARNING "Read Register: address %lu value %lu\n", \
(address), (value)); \
} while (0)
#else

#if 1

#define SEP_WRITE_REGISTER(address, value) writel((value), (void *)(address))
#define SEP_READ_REGISTER(address, value) (value) = readl((void *)(address))
#endif

#endif

#if 0
#define SEP_WRITE_ROM(address, value) writel((value), (void *)(address))

#define SEP_WRITE_REGISTER(address, value) \
do { \
unsigned long i; \
for (i = 0; i < 1000; i++); \
writel((value), (void *)(address)); \
} while (0)


#define SEP_READ_REGISTER(address , value) \
do { \
unsigned long i; \
for (i = 0; i < 1000; i++); \
(value) = readl((void *) (address)); \
} while (0)

#endif

/* wait for SRAM write complete(indirect write */
#define SEP_WAIT_SRAM_WRITE_COMPLETE() \
do { \
unsigned long reg_val; \
do { \
SEP_READ_REGISTER(sep_dev->reg_base_address + \
HW_SRAM_DATA_READY_REG_ADDR, (reg_val)); \
} while (!(reg_val & 0x1)); \
} while (0)

#endif
34 changes: 13 additions & 21 deletions trunk/drivers/staging/sep/sep_ext_with_pci_driver.c
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Original file line number Diff line number Diff line change
Expand Up @@ -424,7 +424,7 @@ static int __devinit sep_probe(struct pci_dev *pdev,
"SEP Driver:io_memory_start_virtual_address is %p\n",
sep_dev->io_memory_start_virtual_address);

sep_dev->reg_base_address = (unsigned long)sep_dev->io_memory_start_virtual_address;
sep_dev->reg_base_address = (void __iomem *)sep_dev->io_memory_start_virtual_address;


/* set up system base address and shared memory location */
Expand Down Expand Up @@ -455,11 +455,11 @@ static int __devinit sep_probe(struct pci_dev *pdev,
"SEP Driver: about to write IMR and ICR REG_ADDR\n");

/* clear ICR register */
SEP_WRITE_REGISTER(sep_dev->reg_base_address + HW_HOST_ICR_REG_ADDR,
sep_write_reg(sep_dev, HW_HOST_ICR_REG_ADDR,
0xFFFFFFFF);

/* set the IMR register - open only GPR 2 */
SEP_WRITE_REGISTER(sep_dev->reg_base_address + HW_HOST_IMR_REG_ADDR,
sep_write_reg(sep_dev, HW_HOST_IMR_REG_ADDR,
(~(0x1 << 13)));

/* figure out our irq */
Expand All @@ -482,7 +482,7 @@ static int __devinit sep_probe(struct pci_dev *pdev,
"SEP Driver: about to write IMR REG_ADDR");

/* set the IMR register - open only GPR 2 */
SEP_WRITE_REGISTER(sep_dev->reg_base_address + HW_HOST_IMR_REG_ADDR,
sep_write_reg(sep_dev, HW_HOST_IMR_REG_ADDR,
(~(0x1 << 13)));

#endif /* SEP_DRIVER_POLLING_MODE */
Expand Down Expand Up @@ -529,11 +529,10 @@ void sep_load_rom_code(void)

for (i = 0; i < 4; i++) {
/* write bank */
SEP_WRITE_REGISTER(sep_dev->reg_base_address
+ SEP_ROM_BANK_register_offset, i);
sep_write_reg(sep_dev, SEP_ROM_BANK_register_offset, i);

for (j = 0; j < CRYS_SEP_ROM_length / 4; j++) {
SEP_WRITE_REGISTER(sep_dev->reg_base_address +
sep_write_reg(sep_dev,
CRYS_SEP_ROM_start_address_offset + 4*j,
CRYS_SEP_ROM[i * 0x1000 + j]);

Expand All @@ -547,13 +546,11 @@ void sep_load_rom_code(void)
}

/* reset the SEP*/
SEP_WRITE_REGISTER(sep_dev->reg_base_address
+ HW_HOST_SEP_SW_RST_REG_ADDR, 0x1);
sep_write_reg(sep_dev, HW_HOST_SEP_SW_RST_REG_ADDR, 0x1);

/* poll for SEP ROM boot finish */
do {
SEP_READ_REGISTER(sep_dev->reg_base_address
+ HW_HOST_SEP_HOST_GPR3_REG_ADDR, regVal);
retVal = sep_read_reg(sep_dev, HW_HOST_SEP_HOST_GPR3_REG_ADDR);
} while (!regVal);

DEBUG_PRINT_0(SEP_DEBUG_LEVEL_EXTENDED,
Expand All @@ -562,38 +559,33 @@ void sep_load_rom_code(void)
switch (regVal) {
case 0x1:
/* fatal error - read erro status from GPRO */
SEP_READ_REGISTER(sep_dev->reg_base_address
+ HW_HOST_SEP_HOST_GPR0_REG_ADDR, Error);
Error = sep_read_reg(sep_dev, HW_HOST_SEP_HOST_GPR0_REG_ADDR);
DEBUG_PRINT_0(SEP_DEBUG_LEVEL_EXTENDED,
"SEP Driver: ROM polling case 1\n");
break;
case 0x2:
/* Boot First Phase ended */
SEP_READ_REGISTER(sep_dev->reg_base_address
+ HW_HOST_SEP_HOST_GPR0_REG_ADDR, warning);
warning = sep_read_reg(sep_dev, HW_HOST_SEP_HOST_GPR0_REG_ADDR);
DEBUG_PRINT_0(SEP_DEBUG_LEVEL_EXTENDED,
"SEP Driver: ROM polling case 2\n");
break;
case 0x4:
/* Cold boot ended successfully */
SEP_READ_REGISTER(sep_dev->reg_base_address
+ HW_HOST_SEP_HOST_GPR0_REG_ADDR, warning);
warning = sep_read_reg(sep_dev, HW_HOST_SEP_HOST_GPR0_REG_ADDR);
DEBUG_PRINT_0(SEP_DEBUG_LEVEL_EXTENDED,
"SEP Driver: ROM polling case 4\n");
Error = 0;
break;
case 0x8:
/* Warmboot ended successfully */
SEP_READ_REGISTER(sep_dev->reg_base_address
+ HW_HOST_SEP_HOST_GPR0_REG_ADDR, warning);
warning = sep_read_reg(sep_dev, HW_HOST_SEP_HOST_GPR0_REG_ADDR);
DEBUG_PRINT_0(SEP_DEBUG_LEVEL_EXTENDED,
"SEP Driver: ROM polling case 8\n");
Error = 0;
break;
case 0x10:
/* ColdWarm boot ended successfully */
SEP_READ_REGISTER(sep_dev->reg_base_address
+ HW_HOST_SEP_HOST_GPR0_REG_ADDR, warning);
warning = sep_read_reg(sep_dev, HW_HOST_SEP_HOST_GPR0_REG_ADDR);
DEBUG_PRINT_0(SEP_DEBUG_LEVEL_EXTENDED,
"SEP Driver: ROM polling case 16\n");
Error = 0;
Expand Down
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