netxen: cache align register map table

Aligning register offset translation table imporves performance on rx side. Signed-off-by: Dhananjay Phadke <dhananjay@netxen.com> Signed-off-by: David S. Miller <davem@davemloft.net>
git-mirror · Apr 8, 2009 · ea7eaa3 · ea7eaa3
1 parent a92e9e6
commit ea7eaa3
Showing 1 changed file with 2 additions and 1 deletion.
diff --git a/drivers/net/netxen/netxen_nic_hw.c b/drivers/net/netxen/netxen_nic_hw.c
@@ -89,7 +89,8 @@ static void __iomem *pci_base_offset(struct netxen_adapter *adapter,
 }
 
 #define CRB_WIN_LOCK_TIMEOUT 100000000
-static crb_128M_2M_block_map_t crb_128M_2M_map[64] = {
+static crb_128M_2M_block_map_t
+crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
     {{{0, 0,         0,         0} } },		/* 0: PCI */
     {{{1, 0x0100000, 0x0102000, 0x120000},	/* 1: PCIE */
 	  {1, 0x0110000, 0x0120000, 0x130000},