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ARM: DRA7: Provide proper IO map table
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DRA7 uses OMAP5 IO table at the moment. This is purely spurious since
the OMAP5 and DRA7 register maps are different in many aspects.

AM57xx/DRA7 TRM Reference: http://www.ti.com/lit/ug/spruhz6/spruhz6.pdf

NOTE: Most of the drivers are already doing ioremap, so, there should'nt
be any functional improvement involved here, other than making the
initial iotable more accurate.

Fixes: a3a9384 ("ARM: DRA7: Reuse io tables and add a new .init_early")
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Nishanth Menon authored and Tony Lindgren committed Jul 16, 2015
1 parent d1dabab commit ea827ad
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Showing 5 changed files with 130 additions and 4 deletions.
4 changes: 2 additions & 2 deletions arch/arm/mach-omap2/board-generic.c
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Original file line number Diff line number Diff line change
Expand Up @@ -297,7 +297,7 @@ static const char *const dra74x_boards_compat[] __initconst = {
DT_MACHINE_START(DRA74X_DT, "Generic DRA74X (Flattened Device Tree)")
.reserve = omap_reserve,
.smp = smp_ops(omap4_smp_ops),
.map_io = omap5_map_io,
.map_io = dra7xx_map_io,
.init_early = dra7xx_init_early,
.init_late = dra7xx_init_late,
.init_irq = omap_gic_of_init,
Expand All @@ -316,7 +316,7 @@ static const char *const dra72x_boards_compat[] __initconst = {

DT_MACHINE_START(DRA72X_DT, "Generic DRA72X (Flattened Device Tree)")
.reserve = omap_reserve,
.map_io = omap5_map_io,
.map_io = dra7xx_map_io,
.init_early = dra7xx_init_early,
.init_late = dra7xx_init_late,
.init_irq = omap_gic_of_init,
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1 change: 1 addition & 0 deletions arch/arm/mach-omap2/common.h
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Original file line number Diff line number Diff line change
Expand Up @@ -198,6 +198,7 @@ void __init omap3_map_io(void);
void __init am33xx_map_io(void);
void __init omap4_map_io(void);
void __init omap5_map_io(void);
void __init dra7xx_map_io(void);
void __init ti81xx_map_io(void);

/**
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58 changes: 56 additions & 2 deletions arch/arm/mach-omap2/io.c
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Original file line number Diff line number Diff line change
Expand Up @@ -236,7 +236,7 @@ static struct map_desc omap44xx_io_desc[] __initdata = {
};
#endif

#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
#ifdef CONFIG_SOC_OMAP5
static struct map_desc omap54xx_io_desc[] __initdata = {
{
.virtual = L3_54XX_VIRT,
Expand Down Expand Up @@ -265,6 +265,53 @@ static struct map_desc omap54xx_io_desc[] __initdata = {
};
#endif

#ifdef CONFIG_SOC_DRA7XX
static struct map_desc dra7xx_io_desc[] __initdata = {
{
.virtual = L4_CFG_MPU_DRA7XX_VIRT,
.pfn = __phys_to_pfn(L4_CFG_MPU_DRA7XX_PHYS),
.length = L4_CFG_MPU_DRA7XX_SIZE,
.type = MT_DEVICE,
},
{
.virtual = L3_MAIN_SN_DRA7XX_VIRT,
.pfn = __phys_to_pfn(L3_MAIN_SN_DRA7XX_PHYS),
.length = L3_MAIN_SN_DRA7XX_SIZE,
.type = MT_DEVICE,
},
{
.virtual = L4_PER1_DRA7XX_VIRT,
.pfn = __phys_to_pfn(L4_PER1_DRA7XX_PHYS),
.length = L4_PER1_DRA7XX_SIZE,
.type = MT_DEVICE,
},
{
.virtual = L4_PER2_DRA7XX_VIRT,
.pfn = __phys_to_pfn(L4_PER2_DRA7XX_PHYS),
.length = L4_PER2_DRA7XX_SIZE,
.type = MT_DEVICE,
},
{
.virtual = L4_PER3_DRA7XX_VIRT,
.pfn = __phys_to_pfn(L4_PER3_DRA7XX_PHYS),
.length = L4_PER3_DRA7XX_SIZE,
.type = MT_DEVICE,
},
{
.virtual = L4_CFG_DRA7XX_VIRT,
.pfn = __phys_to_pfn(L4_CFG_DRA7XX_PHYS),
.length = L4_CFG_DRA7XX_SIZE,
.type = MT_DEVICE,
},
{
.virtual = L4_WKUP_DRA7XX_VIRT,
.pfn = __phys_to_pfn(L4_WKUP_DRA7XX_PHYS),
.length = L4_WKUP_DRA7XX_SIZE,
.type = MT_DEVICE,
},
};
#endif

#ifdef CONFIG_SOC_OMAP2420
void __init omap242x_map_io(void)
{
Expand Down Expand Up @@ -309,12 +356,19 @@ void __init omap4_map_io(void)
}
#endif

#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
#ifdef CONFIG_SOC_OMAP5
void __init omap5_map_io(void)
{
iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
}
#endif

#ifdef CONFIG_SOC_DRA7XX
void __init dra7xx_map_io(void)
{
iotable_init(dra7xx_io_desc, ARRAY_SIZE(dra7xx_io_desc));
}
#endif
/*
* omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
*
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63 changes: 63 additions & 0 deletions arch/arm/mach-omap2/iomap.h
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Original file line number Diff line number Diff line change
Expand Up @@ -194,3 +194,66 @@
#define L4_PER_54XX_PHYS L4_PER_54XX_BASE /* 0x48000000 --> 0xfa000000 */
#define L4_PER_54XX_VIRT (L4_PER_54XX_PHYS + OMAP2_L4_IO_OFFSET)
#define L4_PER_54XX_SIZE SZ_4M

/*
* ----------------------------------------------------------------------------
* DRA7xx specific IO mapping
* ----------------------------------------------------------------------------
*/
/*
* L3_MAIN_SN_DRA7XX_PHYS 0x44000000 --> 0xf8000000
* The overall space is 24MiB (0x4400_0000<->0x457F_FFFF), but mapping
* everything is just inefficient, since, there are too many address holes.
*/
#define L3_MAIN_SN_DRA7XX_PHYS L3_MAIN_SN_DRA7XX_BASE
#define L3_MAIN_SN_DRA7XX_VIRT (L3_MAIN_SN_DRA7XX_PHYS + OMAP4_L3_IO_OFFSET)
#define L3_MAIN_SN_DRA7XX_SIZE SZ_1M

/*
* L4_PER1_DRA7XX_PHYS (0x4800_000<>0x480D_2FFF) -> 0.82MiB (alloc 1MiB)
* (0x48000000<->0x48100000) <=> (0xFA000000<->0xFA100000)
*/
#define L4_PER1_DRA7XX_PHYS L4_PER1_DRA7XX_BASE
#define L4_PER1_DRA7XX_VIRT (L4_PER1_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET)
#define L4_PER1_DRA7XX_SIZE SZ_1M

/*
* L4_CFG_MPU_DRA7XX_PHYS (0x48210000<>0x482A_F2FF) -> 0.62MiB (alloc 1MiB)
* (0x48210000<->0x48310000) <=> (0xFA210000<->0xFA310000)
* NOTE: This is a bit of an orphan memory map sitting isolated in TRM
*/
#define L4_CFG_MPU_DRA7XX_PHYS L4_CFG_MPU_DRA7XX_BASE
#define L4_CFG_MPU_DRA7XX_VIRT (L4_CFG_MPU_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET)
#define L4_CFG_MPU_DRA7XX_SIZE SZ_1M

/*
* L4_PER2_DRA7XX_PHYS (0x4840_0000<>0x4848_8FFF) -> .53MiB (alloc 1MiB)
* (0x48400000<->0x48500000) <=> (0xFA400000<->0xFA500000)
*/
#define L4_PER2_DRA7XX_PHYS L4_PER2_DRA7XX_BASE
#define L4_PER2_DRA7XX_VIRT (L4_PER2_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET)
#define L4_PER2_DRA7XX_SIZE SZ_1M

/*
* L4_PER3_DRA7XX_PHYS (0x4880_0000<>0x489E_0FFF) -> 1.87MiB (alloc 2MiB)
* (0x48800000<->0x48A00000) <=> (0xFA800000<->0xFAA00000)
*/
#define L4_PER3_DRA7XX_PHYS L4_PER3_DRA7XX_BASE
#define L4_PER3_DRA7XX_VIRT (L4_PER3_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET)
#define L4_PER3_DRA7XX_SIZE SZ_2M

/*
* L4_CFG_DRA7XX_PHYS (0x4A00_0000<>0x4A22_BFFF) ->2.17MiB (alloc 3MiB)?
* (0x4A000000<->0x4A300000) <=> (0xFC000000<->0xFC300000)
*/
#define L4_CFG_DRA7XX_PHYS L4_CFG_DRA7XX_BASE
#define L4_CFG_DRA7XX_VIRT (L4_CFG_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET)
#define L4_CFG_DRA7XX_SIZE (SZ_1M + SZ_2M)

/*
* L4_WKUP_DRA7XX_PHYS (0x4AE0_0000<>0x4AE3_EFFF) -> .24 mb (alloc 1MiB)?
* (0x4AE00000<->4AF00000) <=> (0xFCE00000<->0xFCF00000)
*/
#define L4_WKUP_DRA7XX_PHYS L4_WKUP_DRA7XX_BASE
#define L4_WKUP_DRA7XX_VIRT (L4_WKUP_DRA7XX_PHYS + OMAP2_L4_IO_OFFSET)
#define L4_WKUP_DRA7XX_SIZE SZ_1M
8 changes: 8 additions & 0 deletions arch/arm/mach-omap2/omap54xx.h
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Original file line number Diff line number Diff line change
Expand Up @@ -30,6 +30,14 @@
#define OMAP54XX_CTRL_BASE 0x4a002800
#define OMAP54XX_SAR_RAM_BASE 0x4ae26000

/* DRA7 specific base addresses */
#define L3_MAIN_SN_DRA7XX_BASE 0x44000000
#define L4_PER1_DRA7XX_BASE 0x48000000
#define L4_CFG_MPU_DRA7XX_BASE 0x48210000
#define L4_PER2_DRA7XX_BASE 0x48400000
#define L4_PER3_DRA7XX_BASE 0x48800000
#define L4_CFG_DRA7XX_BASE 0x4A000000
#define L4_WKUP_DRA7XX_BASE 0x4ae00000
#define DRA7XX_CM_CORE_AON_BASE 0x4a005000
#define DRA7XX_CTRL_BASE 0x4a003400
#define DRA7XX_TAP_BASE 0x4ae0c000
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