---

yaml
---
r: 216887
b: refs/heads/master
c: ca82876
h: refs/heads/master
i:
  216885: b0a9d39
  216883: 6b034b1
  216879: 5530eda
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 5a37e7840f445b551b8bdba3b4f10f7ea365dcfc
+refs/heads/master: ca828760f96ee8f0b6c93400599844761aa69dc0

trunk/arch/arm/mach-omap2/board-omap4panda.c

@@ -274,8 +274,6 @@ static int __init omap4_panda_i2c_init(void)
 }
 static void __init omap4_panda_init(void)
 {
-	int status;
-
 	omap4_panda_i2c_init();
 	omap_serial_init();
 	omap4_twl6030_hsmmc_init(mmc);

trunk/arch/arm/mach-omap2/id.c

@@ -298,6 +298,7 @@ static void __init omap4_check_revision(void)
 	u32 idcode;
 	u16 hawkeye;
 	u8 rev;
+	char *rev_name = "ES1.0";
 
 	/*
 	 * The IC rev detection is done with hawkeye and rev.
@@ -308,39 +309,14 @@ static void __init omap4_check_revision(void)
 	hawkeye = (idcode >> 12) & 0xffff;
 	rev = (idcode >> 28) & 0xff;
 
-	/*
-	 * Few initial ES2.0 samples IDCODE is same as ES1.0
-	 * Use ARM register to detect the correct ES version
-	 */
-	if (!rev) {
-		idcode = read_cpuid(CPUID_ID);
-		rev = (idcode & 0xf) - 1;
-	}
-
-	switch (hawkeye) {
-	case 0xb852:
-		switch (rev) {
-		case 0:
-			omap_revision = OMAP4430_REV_ES1_0;
-			omap_chip.oc |= CHIP_IS_OMAP4430ES1;
-			break;
-		case 1:
-			omap_revision = OMAP4430_REV_ES2_0;
-			omap_chip.oc |= CHIP_IS_OMAP4430ES2;
-			break;
-		default:
-			omap_revision = OMAP4430_REV_ES2_0;
-			omap_chip.oc |= CHIP_IS_OMAP4430ES2;
-	}
-	break;
-	default:
-		/* Unknown default to latest silicon rev as default*/
-		omap_revision = OMAP4430_REV_ES2_0;
-		omap_chip.oc |= CHIP_IS_OMAP4430ES2;
+	if ((hawkeye == 0xb852) && (rev == 0x0)) {
+		omap_revision = OMAP4430_REV_ES1_0;
+		omap_chip.oc |= CHIP_IS_OMAP4430ES1;
+		pr_info("OMAP%04x %s\n", omap_rev() >> 16, rev_name);
+		return;
 	}
 
-	pr_info("OMAP%04x ES%d.0\n",
-			omap_rev() >> 16, ((omap_rev() >> 12) & 0xf) + 1);
+	pr_err("Unknown OMAP4 CPU id\n");
 }
 
 #define OMAP3_SHOW_FEATURE(feat)		\

trunk/arch/arm/mach-omap2/mux.c

@@ -87,7 +87,7 @@ static char *omap_mux_options;
 int __init omap_mux_init_gpio(int gpio, int val)
 {
 	struct omap_mux_entry *e;
-	struct omap_mux *gpio_mux;
+	struct omap_mux *gpio_mux = NULL;
 	u16 old_mode;
 	u16 mux_mode;
 	int found = 0;

trunk/arch/arm/mach-omap2/omap4-common.c

@@ -61,14 +61,10 @@ static int __init omap_l2_cache_init(void)
 	omap_smc1(0x102, 0x1);
 
 	/*
-	 * 16-way associativity, parity disabled
-	 * Way size - 32KB (es1.0)
-	 * Way size - 64KB (es2.0 +)
+	 * 32KB way size, 16-way associativity,
+	 * parity disabled
 	 */
-	if (omap_rev() == OMAP4430_REV_ES1_0)
-		l2x0_init(l2cache_base, 0x0e050000, 0xc0000fff);
-	else
-		l2x0_init(l2cache_base, 0x0e070000, 0xc0000fff);
+	l2x0_init(l2cache_base, 0x0e050000, 0xc0000fff);
 
 	return 0;
 }

trunk/arch/arm/plat-omap/dmtimer.c

@@ -581,7 +581,7 @@ int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
 	 * When the functional clock disappears, too quick writes seem
 	 * to cause an abort. XXX Is this still necessary?
 	 */
-	__delay(300000);
+	__delay(150000);
 
 	return ret;
 }

trunk/arch/arm/plat-omap/gpio.c

@@ -2084,7 +2084,7 @@ void omap2_gpio_prepare_for_idle(int power_state)
 
 	for (i = min; i < gpio_bank_count; i++) {
 		struct gpio_bank *bank = &gpio_bank[i];
-		u32 l1, l2;
+		u32 l1 = 0, l2 = 0;
 		int j;
 
 		for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
@@ -2152,7 +2152,7 @@ void omap2_gpio_resume_after_idle(void)
 		min = 1;
 	for (i = min; i < gpio_bank_count; i++) {
 		struct gpio_bank *bank = &gpio_bank[i];
-		u32 l, gen, gen0, gen1;
+		u32 l = 0, gen, gen0, gen1;
 		int j;
 
 		for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)

trunk/arch/arm/plat-omap/include/plat/cpu.h

@@ -391,7 +391,6 @@ IS_OMAP_TYPE(3517, 0x3517)
 
 #define OMAP443X_CLASS		0x44300044
 #define OMAP4430_REV_ES1_0	0x44300044
-#define OMAP4430_REV_ES2_0	0x44301044
 
 /*
  * omap_chip bits
@@ -418,12 +417,10 @@ IS_OMAP_TYPE(3517, 0x3517)
 #define CHIP_IS_OMAP4430ES1		(1 << 8)
 #define CHIP_IS_OMAP3630ES1_1           (1 << 9)
 #define CHIP_IS_OMAP3630ES1_2           (1 << 10)
-#define CHIP_IS_OMAP4430ES2		(1 << 11)
 
 #define CHIP_IS_OMAP24XX		(CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
 
-#define CHIP_IS_OMAP4430		(CHIP_IS_OMAP4430ES1 | \
-						 CHIP_IS_OMAP4430ES2)
+#define CHIP_IS_OMAP4430		(CHIP_IS_OMAP4430ES1)
 
 /*
  * "GE" here represents "greater than or equal to" in terms of ES

trunk/arch/arm/plat-omap/include/plat/uncompress.h

@@ -153,7 +153,6 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
 
 		/* omap4 based boards using UART3 */
 		DEBUG_LL_OMAP4(3, omap_4430sdp);
-		DEBUG_LL_OMAP4(3, omap4_panda);
 
 		/* zoom2/3 external uart */
 		DEBUG_LL_ZOOM(omap_zoom2);

trunk/arch/arm/plat-omap/sram.c

@@ -53,7 +53,7 @@
 #define OMAP4_SRAM_PUB_PA	(OMAP4_SRAM_PA + 0x4000)
 #define OMAP4_SRAM_PUB_VA	(OMAP4_SRAM_VA + 0x4000)
 
-#if defined(CONFIG_ARCH_OMAP2PLUS)
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
 #define SRAM_BOOTLOADER_SZ	0x00
 #else
 #define SRAM_BOOTLOADER_SZ	0x80
@@ -93,7 +93,16 @@ extern unsigned long omapfb_reserve_sram(unsigned long sram_pstart,
  */
 static int is_sram_locked(void)
 {
-	if (OMAP2_DEVICE_TYPE_GP == omap_type()) {
+	int type = 0;
+
+	if (cpu_is_omap44xx())
+		/* Not yet supported */
+		return 0;
+
+	if (cpu_is_omap242x())
+		type = omap_rev() & OMAP2_DEVICETYPE_MASK;
+
+	if (type == GP_DEVICE) {
 		/* RAMFW: R/W access to all initiators for all qualifier sets */
 		if (cpu_is_omap242x()) {
 			__raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */