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drm/nvc8/gr: update initial register/context values
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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs committed Jul 1, 2013
1 parent dba5072 commit eb12f57
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Showing 6 changed files with 74 additions and 10 deletions.
28 changes: 28 additions & 0 deletions drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1329,6 +1329,7 @@ nvc0_grctx_generate_9097(struct nvc0_graph_priv *priv)
case 0xc3:
case 0xc4:
case 0xc1:
case 0xc8:
case 0xd9:
case 0xd7:
break;
Expand Down Expand Up @@ -1479,6 +1480,7 @@ nvc0_grctx_generate_dispatch(struct nvc0_graph_priv *priv)
case 0xc3:
case 0xc4:
case 0xc1:
case 0xc8:
default:
break;
}
Expand All @@ -1502,6 +1504,7 @@ nvc0_grctx_generate_dispatch(struct nvc0_graph_priv *priv)
case 0xc3:
case 0xc4:
case 0xc1:
case 0xc8:
case 0xd9:
case 0xd7:
nv_wr32(priv, 0x4040d0, 0x00000000);
Expand Down Expand Up @@ -1532,6 +1535,7 @@ nvc0_grctx_generate_dispatch(struct nvc0_graph_priv *priv)
case 0xc3:
case 0xc4:
case 0xc1:
case 0xc8:
default:
nv_wr32(priv, 0x404174, 0x00000000);
break;
Expand Down Expand Up @@ -1676,6 +1680,7 @@ nvc0_grctx_generate_shaders(struct nvc0_graph_priv *priv)
case 0xc0:
case 0xc3:
case 0xc4:
case 0xc8:
default:
nv_wr32(priv, 0x405800, 0x078000bf);
nv_wr32(priv, 0x405830, 0x02180000);
Expand Down Expand Up @@ -1720,6 +1725,7 @@ nvc0_grctx_generate_unk64xx(struct nvc0_graph_priv *priv)
case 0xc3:
case 0xc4:
case 0xc1:
case 0xc8:
default:
break;
}
Expand All @@ -1733,6 +1739,7 @@ nvc0_grctx_generate_unk64xx(struct nvc0_graph_priv *priv)
case 0xc0:
case 0xc3:
case 0xc4:
case 0xc8:
default:
break;
}
Expand Down Expand Up @@ -1774,6 +1781,7 @@ nvc0_grctx_generate_rop(struct nvc0_graph_priv *priv)
case 0xc0:
case 0xc3:
case 0xc4:
case 0xc8:
nv_wr32(priv, 0x408808, 0x0003e00d);
nv_wr32(priv, 0x408900, 0x3080b801);
nv_wr32(priv, 0x408904, 0x02000001);
Expand Down Expand Up @@ -1820,6 +1828,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
case 0xc3:
case 0xc4:
case 0xc1:
case 0xc8:
default:
nv_wr32(priv, 0x418408, 0x00000000);
break;
Expand All @@ -1835,6 +1844,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
case 0xc3:
case 0xc4:
case 0xc1:
case 0xc8:
default:
nv_wr32(priv, 0x418414, 0x00200fff);
break;
Expand Down Expand Up @@ -1862,6 +1872,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
case 0xc3:
case 0xc4:
case 0xc1:
case 0xc8:
default:
nv_wr32(priv, 0x41870c, 0x07c80000);
break;
Expand All @@ -1876,6 +1887,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
case 0xc3:
case 0xc4:
case 0xc1:
case 0xc8:
default:
nv_wr32(priv, 0x418800, 0x0006860a);
break;
Expand All @@ -1893,6 +1905,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
case 0xc0:
case 0xc3:
case 0xc4:
case 0xc8:
default:
nv_wr32(priv, 0x418830, 0x00000001);
break;
Expand All @@ -1915,6 +1928,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
case 0xc0:
case 0xc3:
case 0xc4:
case 0xc8:
default:
nv_wr32(priv, 0x4188fc, 0x00100000);
break;
Expand All @@ -1941,6 +1955,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
case 0xc3:
case 0xc4:
case 0xc1:
case 0xc8:
default:
nv_wr32(priv, 0x418b00, 0x00000000);
break;
Expand Down Expand Up @@ -1970,6 +1985,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
case 0xc0:
case 0xc3:
case 0xc4:
case 0xc8:
default:
break;
}
Expand Down Expand Up @@ -1997,6 +2013,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
case 0xc0:
case 0xc3:
case 0xc4:
case 0xc8:
default:
nv_wr32(priv, 0x419864, 0x0000012a);
break;
Expand All @@ -2014,6 +2031,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
case 0xc3:
case 0xc4:
case 0xc1:
case 0xc8:
default:
nv_wr32(priv, 0x419a1c, 0x00000000);
nv_wr32(priv, 0x419a20, 0x00000800);
Expand Down Expand Up @@ -2050,6 +2068,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
case 0xc0:
case 0xc3:
case 0xc4:
case 0xc8:
default:
nv_wr32(priv, 0x419be0, 0x00000001);
break;
Expand All @@ -2064,6 +2083,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
case 0xc3:
case 0xc4:
case 0xc1:
case 0xc8:
default:
nv_wr32(priv, 0x419c00, 0x00000002);
break;
Expand All @@ -2086,6 +2106,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
nv_wr32(priv, 0x419cb0, 0x00020048);
break;
case 0xc0:
case 0xc8:
default:
nv_wr32(priv, 0x419cb0, 0x00060048);
break;
Expand All @@ -2101,6 +2122,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
case 0xc0:
case 0xc3:
case 0xc4:
case 0xc8:
default:
nv_wr32(priv, 0x419d20, 0x02180000);
break;
Expand All @@ -2115,6 +2137,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
case 0xc0:
case 0xc3:
case 0xc4:
case 0xc8:
default:
break;
}
Expand Down Expand Up @@ -2506,6 +2529,7 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
case 0xc3:
case 0xc4:
case 0xc1:
case 0xc8:
default:
break;
}
Expand All @@ -2527,6 +2551,7 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
case 0xc3:
case 0xc4:
case 0xc1:
case 0xc8:
break;
default:
break;
Expand Down Expand Up @@ -3095,6 +3120,7 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
nv_icmd(priv, 0x00000576, 0x00000003);
switch (nv_device(priv)->chipset) {
case 0xc1:
case 0xc8:
case 0xd9:
case 0xd7:
nv_icmd(priv, 0x0000057b, 0x00000059);
Expand Down Expand Up @@ -3208,6 +3234,7 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
switch (nv_device(priv)->chipset) {
case 0xd9:
case 0xd7:
case 0xc8:
nv_icmd(priv, 0x0000097d, 0x00000020);
break;
case 0xc0:
Expand Down Expand Up @@ -3364,6 +3391,7 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
case 0xc3:
case 0xc4:
case 0xc1:
case 0xc8:
nv_mthd(priv, 0x902d, 0x3410, 0x00000000);
break;
case 0xd9:
Expand Down
8 changes: 4 additions & 4 deletions drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc
View file
Original file line number Diff line number Diff line change
Expand Up @@ -68,10 +68,10 @@ chipsets:
.b16 #nnvc3_tpc_mmio_head
.b16 #nnvc3_tpc_mmio_tail
.b8 0xc8 0 0 0
.b16 #nvc0_gpc_mmio_head
.b16 #nvc0_gpc_mmio_tail
.b16 #nvc0_tpc_mmio_head
.b16 #nvc0_tpc_mmio_tail
.b16 #nnvc0_gpc_mmio_head
.b16 #nnvc0_gpc_mmio_tail
.b16 #nnvc0_tpc_mmio_head
.b16 #nnvc0_tpc_mmio_tail
.b8 0xce 0 0 0
.b16 #nvc0_gpc_mmio_head
.b16 #nvc0_gpc_mmio_tail
Expand Down
4 changes: 2 additions & 2 deletions drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -46,8 +46,8 @@ uint32_t nvc0_grgpc_data[] = {
0x01940134,
0x030402ac,
0x000000c8,
0x013400d4,
0x02500200,
0x01940134,
0x02ac0260,
0x000000ce,
0x013400d4,
0x02600200,
Expand Down
4 changes: 2 additions & 2 deletions drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc
View file
Original file line number Diff line number Diff line change
Expand Up @@ -60,8 +60,8 @@ chipsets:
.b16 #nnvc0_hub_mmio_head
.b16 #nnvc0_hub_mmio_tail
.b8 0xc8 0 0 0
.b16 #nvc0_hub_mmio_head
.b16 #nvc0_hub_mmio_tail
.b16 #nnvc0_hub_mmio_head
.b16 #nnvc0_hub_mmio_tail
.b8 0xce 0 0 0
.b16 #nvc0_hub_mmio_head
.b16 #nvc0_hub_mmio_tail
Expand Down
2 changes: 1 addition & 1 deletion drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -211,7 +211,7 @@ uint32_t nvc0_grhub_data[] = {
0x000000c4,
0x048403e8,
0x000000c8,
0x03e8034c,
0x048403e8,
0x000000ce,
0x03e8034c,
0x000000cf,
Expand Down
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