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yaml
---
r: 260625
b: refs/heads/master
c: e4cf2d1
h: refs/heads/master
i:
  260623: eeb5049
v: v3
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Jaecheol Lee authored and Kukjin Kim committed Jul 20, 2011
1 parent dbaf570 commit ec88cf0
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2 changes: 1 addition & 1 deletion [refs]
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@@ -1,2 +1,2 @@
---
refs/heads/master: e28e301475f373b4c4361a47c83da20c951c2201
refs/heads/master: e4cf2d1495fc6030c6b01e266aaa125061f58d5b
77 changes: 2 additions & 75 deletions trunk/arch/arm/mach-exynos4/pm.c
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Expand Up @@ -30,80 +30,7 @@
#include <mach/regs-clock.h>
#include <mach/regs-pmu.h>
#include <mach/pm-core.h>

static struct sleep_save exynos4_sleep[] = {
{ .reg = S5P_ARM_CORE0_LOWPWR , .val = 0x2, },
{ .reg = S5P_DIS_IRQ_CORE0 , .val = 0x0, },
{ .reg = S5P_DIS_IRQ_CENTRAL0 , .val = 0x0, },
{ .reg = S5P_ARM_CORE1_LOWPWR , .val = 0x2, },
{ .reg = S5P_DIS_IRQ_CORE1 , .val = 0x0, },
{ .reg = S5P_DIS_IRQ_CENTRAL1 , .val = 0x0, },
{ .reg = S5P_ARM_COMMON_LOWPWR , .val = 0x2, },
{ .reg = S5P_L2_0_LOWPWR , .val = 0x3, },
{ .reg = S5P_L2_1_LOWPWR , .val = 0x3, },
{ .reg = S5P_CMU_ACLKSTOP_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_SCLKSTOP_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_RESET_LOWPWR , .val = 0x0, },
{ .reg = S5P_APLL_SYSCLK_LOWPWR , .val = 0x0, },
{ .reg = S5P_MPLL_SYSCLK_LOWPWR , .val = 0x0, },
{ .reg = S5P_VPLL_SYSCLK_LOWPWR , .val = 0x0, },
{ .reg = S5P_EPLL_SYSCLK_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_RESET_GPSALIVE_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_CLKSTOP_CAM_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_CLKSTOP_TV_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_CLKSTOP_MFC_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_CLKSTOP_G3D_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_CLKSTOP_LCD0_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_CLKSTOP_LCD1_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_CLKSTOP_MAUDIO_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_CLKSTOP_GPS_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_RESET_CAM_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_RESET_TV_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_RESET_MFC_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_RESET_G3D_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_RESET_LCD0_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_RESET_LCD1_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_RESET_MAUDIO_LOWPWR , .val = 0x0, },
{ .reg = S5P_CMU_RESET_GPS_LOWPWR , .val = 0x0, },
{ .reg = S5P_TOP_BUS_LOWPWR , .val = 0x0, },
{ .reg = S5P_TOP_RETENTION_LOWPWR , .val = 0x1, },
{ .reg = S5P_TOP_PWR_LOWPWR , .val = 0x3, },
{ .reg = S5P_LOGIC_RESET_LOWPWR , .val = 0x0, },
{ .reg = S5P_ONENAND_MEM_LOWPWR , .val = 0x0, },
{ .reg = S5P_MODIMIF_MEM_LOWPWR , .val = 0x0, },
{ .reg = S5P_G2D_ACP_MEM_LOWPWR , .val = 0x0, },
{ .reg = S5P_USBOTG_MEM_LOWPWR , .val = 0x0, },
{ .reg = S5P_HSMMC_MEM_LOWPWR , .val = 0x0, },
{ .reg = S5P_CSSYS_MEM_LOWPWR , .val = 0x0, },
{ .reg = S5P_SECSS_MEM_LOWPWR , .val = 0x0, },
{ .reg = S5P_PCIE_MEM_LOWPWR , .val = 0x0, },
{ .reg = S5P_SATA_MEM_LOWPWR , .val = 0x0, },
{ .reg = S5P_PAD_RETENTION_DRAM_LOWPWR , .val = 0x0, },
{ .reg = S5P_PAD_RETENTION_MAUDIO_LOWPWR , .val = 0x0, },
{ .reg = S5P_PAD_RETENTION_GPIO_LOWPWR , .val = 0x0, },
{ .reg = S5P_PAD_RETENTION_UART_LOWPWR , .val = 0x0, },
{ .reg = S5P_PAD_RETENTION_MMCA_LOWPWR , .val = 0x0, },
{ .reg = S5P_PAD_RETENTION_MMCB_LOWPWR , .val = 0x0, },
{ .reg = S5P_PAD_RETENTION_EBIA_LOWPWR , .val = 0x0, },
{ .reg = S5P_PAD_RETENTION_EBIB_LOWPWR , .val = 0x0, },
{ .reg = S5P_PAD_RETENTION_ISOLATION_LOWPWR , .val = 0x0, },
{ .reg = S5P_PAD_RETENTION_ALV_SEL_LOWPWR , .val = 0x0, },
{ .reg = S5P_XUSBXTI_LOWPWR , .val = 0x0, },
{ .reg = S5P_XXTI_LOWPWR , .val = 0x0, },
{ .reg = S5P_EXT_REGULATOR_LOWPWR , .val = 0x0, },
{ .reg = S5P_GPIO_MODE_LOWPWR , .val = 0x0, },
{ .reg = S5P_GPIO_MODE_MAUDIO_LOWPWR , .val = 0x0, },
{ .reg = S5P_CAM_LOWPWR , .val = 0x0, },
{ .reg = S5P_TV_LOWPWR , .val = 0x0, },
{ .reg = S5P_MFC_LOWPWR , .val = 0x0, },
{ .reg = S5P_G3D_LOWPWR , .val = 0x0, },
{ .reg = S5P_LCD0_LOWPWR , .val = 0x0, },
{ .reg = S5P_LCD1_LOWPWR , .val = 0x0, },
{ .reg = S5P_MAUDIO_LOWPWR , .val = 0x0, },
{ .reg = S5P_GPS_LOWPWR , .val = 0x0, },
{ .reg = S5P_GPS_ALIVE_LOWPWR , .val = 0x0, },
};
#include <mach/pmu.h>

static struct sleep_save exynos4_set_clksrc[] = {
{ .reg = S5P_CLKSRC_MASK_TOP , .val = 0x00000001, },
Expand Down Expand Up @@ -331,7 +258,7 @@ static void exynos4_pm_prepare(void)

/* Set value of power down register for sleep mode */

s3c_pm_do_restore_core(exynos4_sleep, ARRAY_SIZE(exynos4_sleep));
exynos4_sys_powerdown_conf(SYS_SLEEP);
__raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);

/* ensure at least INFORM0 has the resume address */
Expand Down

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