---

yaml
---
r: 185529
b: refs/heads/master
c: b5b72e8
h: refs/heads/master
i:
  185527: b7f8925
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: f97108d1d0facc7902134ebc453b226bbd4d1cdb
+refs/heads/master: b5b72e891a5a6056c849ef8eaf259f126090f88b

trunk/drivers/gpu/drm/i915/i915_drv.h

@@ -452,7 +452,7 @@ typedef struct drm_i915_private {
 	u32 savePIPEB_DATA_N1;
 	u32 savePIPEB_LINK_M1;
 	u32 savePIPEB_LINK_N1;
-	u32 saveRSTDBYCTL;
+	u32 saveMCHBAR_RENDER_STANDBY;
 
 	struct {
 		struct drm_mm gtt_space;

trunk/drivers/gpu/drm/i915/i915_irq.c

@@ -272,23 +272,23 @@ static void i915_hotplug_work_func(struct work_struct *work)
 static void i915_handle_rps_change(struct drm_device *dev)
 {
 	drm_i915_private_t *dev_priv = dev->dev_private;
-	u32 slow_up, slow_down, max_avg, min_avg;
+	u32 busy_up, busy_down, max_avg, min_avg;
 	u16 rgvswctl;
 	u8 new_delay = dev_priv->cur_delay;
 
 	I915_WRITE(MEMINTRSTS, I915_READ(MEMINTRSTS) & ~MEMINT_EVAL_CHG);
-	slow_up = I915_READ(RCPREVBSYTUPAVG);
-	slow_down = I915_READ(RCPREVBSYTDNAVG);
+	busy_up = I915_READ(RCPREVBSYTUPAVG);
+	busy_down = I915_READ(RCPREVBSYTDNAVG);
 	max_avg = I915_READ(RCBMAXAVG);
 	min_avg = I915_READ(RCBMINAVG);
 
 	/* Handle RCS change request from hw */
-	if (slow_up > max_avg) {
+	if (busy_up > max_avg) {
 		if (dev_priv->cur_delay != dev_priv->max_delay)
 			new_delay = dev_priv->cur_delay - 1;
 		if (new_delay < dev_priv->max_delay)
 			new_delay = dev_priv->max_delay;
-	} else if (slow_down < min_avg) {
+	} else if (busy_down < min_avg) {
 		if (dev_priv->cur_delay != dev_priv->min_delay)
 			new_delay = dev_priv->cur_delay + 1;
 		if (new_delay > dev_priv->min_delay)
@@ -300,8 +300,8 @@ static void i915_handle_rps_change(struct drm_device *dev)
 
 	rgvswctl = I915_READ(MEMSWCTL);
 	if (rgvswctl & MEMCTL_CMD_STS) {
-		DRM_ERROR("gpu slow, RCS change rejected\n");
-		return; /* still slow with another command */
+		DRM_ERROR("gpu busy, RCS change rejected\n");
+		return; /* still busy with another command */
 	}
 
 	/* Program the new state */

trunk/drivers/gpu/drm/i915/i915_reg.h

@@ -907,7 +907,7 @@
 #define RCBMINAVG		0x111a0
 #define RCUPEI			0x111b0
 #define RCDNEI			0x111b4
-#define RSTDBYCTL		0x111b8
+#define MCHBAR_RENDER_STANDBY		0x111b8
 #define   RCX_SW_EXIT		(1<<23)
 #define   RSX_STATUS_MASK	0x00700000
 #define VIDCTL			0x111c0

trunk/drivers/gpu/drm/i915/i915_suspend.c

@@ -682,7 +682,8 @@ void i915_restore_display(struct drm_device *dev)
 		I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
 		I915_WRITE(PCH_PP_DIVISOR, dev_priv->savePP_DIVISOR);
 		I915_WRITE(PCH_PP_CONTROL, dev_priv->savePP_CONTROL);
-		I915_WRITE(RSTDBYCTL, dev_priv->saveRSTDBYCTL);
+		I915_WRITE(MCHBAR_RENDER_STANDBY,
+			   dev_priv->saveMCHBAR_RENDER_STANDBY);
 	} else {
 		I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);
 		I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
@@ -746,7 +747,8 @@ int i915_save_state(struct drm_device *dev)
 		dev_priv->saveGTIMR = I915_READ(GTIMR);
 		dev_priv->saveFDI_RXA_IMR = I915_READ(FDI_RXA_IMR);
 		dev_priv->saveFDI_RXB_IMR = I915_READ(FDI_RXB_IMR);
-		dev_priv->saveRSTDBYCTL = I915_READ(RSTDBYCTL);
+		dev_priv->saveMCHBAR_RENDER_STANDBY =
+			I915_READ(MCHBAR_RENDER_STANDBY);
 	} else {
 		dev_priv->saveIER = I915_READ(IER);
 		dev_priv->saveIMR = I915_READ(IMR);

trunk/drivers/gpu/drm/i915/intel_display.c

@@ -4770,8 +4770,8 @@ void intel_init_clock_gating(struct drm_device *dev)
 
 		if (obj_priv) {
 			I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
-			I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) &
-				   ~RCX_SW_EXIT);
+			I915_WRITE(MCHBAR_RENDER_STANDBY,
+				   I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
 		}
 	}
 }