---

yaml
---
r: 205966
b: refs/heads/master
c: 38bf20a
h: refs/heads/master
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: c30d6cb7fb587d3dda068f40c629855dfa141652
+refs/heads/master: 38bf20a9b6d6416563f0a261e90fa7081e273dfa

trunk/drivers/staging/tidspbridge/hw/MMURegAcM.h

@@ -17,7 +17,6 @@
 #ifndef _MMU_REG_ACM_H
 #define _MMU_REG_ACM_H
 
-#include <GlobalTypes.h>
 #include <linux/io.h>
 #include <EasiGlobal.h>
 

trunk/drivers/staging/tidspbridge/hw/hw_defs.h

@@ -19,8 +19,6 @@
 #ifndef _HW_DEFS_H
 #define _HW_DEFS_H
 
-#include <GlobalTypes.h>
-
 /* Page size */
 #define HW_PAGE_SIZE4KB   0x1000
 #define HW_PAGE_SIZE64KB  0x10000

trunk/drivers/staging/tidspbridge/hw/hw_mmu.c

@@ -16,7 +16,6 @@
  * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
  */
 
-#include <GlobalTypes.h>
 #include <linux/io.h>
 #include "MMURegAcM.h"
 #include <hw_defs.h>
@@ -250,10 +249,6 @@ hw_status hw_mmu_fault_addr_read(const void __iomem *base_address, u32 *addr)
 {
 	hw_status status = 0;
 
-	/*Check the input Parameters */
-	CHECK_INPUT_PARAM(base_address, 0, RET_BAD_NULL_PARAM,
-			  RES_MMU_BASE + RES_INVALID_INPUT_PARAM);
-
 	/* read values from register */
 	*addr = MMUMMU_FAULT_AD_READ_REGISTER32(base_address);
 
@@ -265,10 +260,6 @@ hw_status hw_mmu_ttb_set(const void __iomem *base_address, u32 ttb_phys_addr)
 	hw_status status = 0;
 	u32 load_ttb;
 
-	/*Check the input Parameters */
-	CHECK_INPUT_PARAM(base_address, 0, RET_BAD_NULL_PARAM,
-			  RES_MMU_BASE + RES_INVALID_INPUT_PARAM);
-
 	load_ttb = ttb_phys_addr & ~0x7FUL;
 	/* write values to register */
 	MMUMMU_TTB_WRITE_REGISTER32(base_address, load_ttb);
@@ -346,14 +337,6 @@ hw_status hw_mmu_tlb_add(const void __iomem *base_address,
 	enum hw_mmu_page_size_t mmu_pg_size;
 
 	/*Check the input Parameters */
-	CHECK_INPUT_PARAM(base_address, 0, RET_BAD_NULL_PARAM,
-			  RES_MMU_BASE + RES_INVALID_INPUT_PARAM);
-	CHECK_INPUT_RANGE_MIN0(page_sz, MMU_PAGE_MAX, RET_PARAM_OUT_OF_RANGE,
-			       RES_MMU_BASE + RES_INVALID_INPUT_PARAM);
-	CHECK_INPUT_RANGE_MIN0(map_attrs->element_size, MMU_ELEMENTSIZE_MAX,
-			       RET_PARAM_OUT_OF_RANGE, RES_MMU_BASE +
-			       RES_INVALID_INPUT_PARAM);
-
 	switch (page_sz) {
 	case HW_PAGE_SIZE4KB:
 		mmu_pg_size = HW_MMU_SMALL_PAGE;
@@ -526,10 +509,6 @@ static hw_status mmu_flush_entry(const void __iomem *base_address)
 	hw_status status = 0;
 	u32 flush_entry_data = 0x1;
 
-	/*Check the input Parameters */
-	CHECK_INPUT_PARAM(base_address, 0, RET_BAD_NULL_PARAM,
-			  RES_MMU_BASE + RES_INVALID_INPUT_PARAM);
-
 	/* write values to register */
 	MMUMMU_FLUSH_ENTRY_WRITE_REGISTER32(base_address, flush_entry_data);
 
@@ -546,10 +525,6 @@ static hw_status mmu_set_cam_entry(const void __iomem *base_address,
 	hw_status status = 0;
 	u32 mmu_cam_reg;
 
-	/*Check the input Parameters */
-	CHECK_INPUT_PARAM(base_address, 0, RET_BAD_NULL_PARAM,
-			  RES_MMU_BASE + RES_INVALID_INPUT_PARAM);
-
 	mmu_cam_reg = (virtual_addr_tag << 12);
 	mmu_cam_reg = (mmu_cam_reg) | (page_sz) | (valid_bit << 2) |
 	    (preserved_bit << 3);
@@ -570,13 +545,6 @@ static hw_status mmu_set_ram_entry(const void __iomem *base_address,
 	hw_status status = 0;
 	u32 mmu_ram_reg;
 
-	/*Check the input Parameters */
-	CHECK_INPUT_PARAM(base_address, 0, RET_BAD_NULL_PARAM,
-			  RES_MMU_BASE + RES_INVALID_INPUT_PARAM);
-	CHECK_INPUT_RANGE_MIN0(element_size, MMU_ELEMENTSIZE_MAX,
-			       RET_PARAM_OUT_OF_RANGE, RES_MMU_BASE +
-			       RES_INVALID_INPUT_PARAM);
-
 	mmu_ram_reg = (physical_addr & MMU_ADDR_MASK);
 	mmu_ram_reg = (mmu_ram_reg) | ((endianism << 9) | (element_size << 7) |
 				       (mixed_size << 6));