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yaml
---
r: 289753
b: refs/heads/master
c: c22610d
h: refs/heads/master
i:
  289751: 4384f1b
v: v3
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Ariel Elior authored and David S. Miller committed Jan 26, 2012
1 parent 915f338 commit ee90683
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Showing 3 changed files with 19 additions and 3 deletions.
2 changes: 1 addition & 1 deletion [refs]
Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: 127a425e8f05b9813879e8ca909ef4338ec8ec04
refs/heads/master: c22610d0001ebf3420d39f419056a56c5aa43096
17 changes: 16 additions & 1 deletion trunk/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
Original file line number Diff line number Diff line change
Expand Up @@ -10546,6 +10546,7 @@ static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
{
struct bnx2x *bp;
int rc;
u32 pci_cfg_dword;
bool chip_is_e1x = (board_type == BCM57710 ||
board_type == BCM57711 ||
board_type == BCM57711E);
Expand All @@ -10556,7 +10557,6 @@ static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
bp->dev = dev;
bp->pdev = pdev;
bp->flags = 0;
bp->pf_num = PCI_FUNC(pdev->devfn);

rc = pci_enable_device(pdev);
if (rc) {
Expand Down Expand Up @@ -10623,6 +10623,21 @@ static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
goto err_out_release;
}

/* In E1/E1H use pci device function given by kernel.
* In E2/E3 read physical function from ME register since these chips
* support Physical Device Assignment where kernel BDF maybe arbitrary
* (depending on hypervisor).
*/
if (chip_is_e1x)
bp->pf_num = PCI_FUNC(pdev->devfn);
else {/* chip is E2/3*/
pci_read_config_dword(bp->pdev,
PCICFG_ME_REGISTER, &pci_cfg_dword);
bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
ME_REG_ABS_PF_NUM_SHIFT);
}
DP(BNX2X_MSG_SP, "me reg PF num: %d\n", bp->pf_num);

bnx2x_set_power_state(bp, PCI_D0);

/* clean indirect addresses */
Expand Down
3 changes: 2 additions & 1 deletion trunk/drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h
Original file line number Diff line number Diff line change
Expand Up @@ -6023,7 +6023,8 @@
#define PCICFG_MSI_CONTROL_64_BIT_ADDR_CAP (0x1<<23)
#define PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE (0x1<<24)
#define PCICFG_GRC_ADDRESS 0x78
#define PCICFG_GRC_DATA 0x80
#define PCICFG_GRC_DATA 0x80
#define PCICFG_ME_REGISTER 0x98
#define PCICFG_MSIX_CAP_ID_OFFSET 0xa0
#define PCICFG_MSIX_CONTROL_TABLE_SIZE (0x7ff<<16)
#define PCICFG_MSIX_CONTROL_RESERVED (0x7<<27)
Expand Down

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