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…benh/powerpc * 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (88 commits) powerpc: Fix lwsync feature fixup vs. modules on 64-bit powerpc: Convert pmc_owner_lock to raw_spinlock powerpc: Convert die.lock to raw_spinlock powerpc: Convert tlbivax_lock to raw_spinlock powerpc: Convert mpic locks to raw_spinlock powerpc: Convert pmac_pic_lock to raw_spinlock powerpc: Convert big_irq_lock to raw_spinlock powerpc: Convert feature_lock to raw_spinlock powerpc: Convert i8259_lock to raw_spinlock powerpc: Convert beat_htab_lock to raw_spinlock powerpc: Convert confirm_error_lock to raw_spinlock powerpc: Convert ipic_lock to raw_spinlock powerpc: Convert native_tlbie_lock to raw_spinlock powerpc: Convert beatic_irq_mask_lock to raw_spinlock powerpc: Convert nv_lock to raw_spinlock powerpc: Convert context_lock to raw_spinlock powerpc/85xx: Add NOR, LEDs and PIB support for MPC8568E-MDS boards powerpc/86xx: Enable VME driver on the GE SBC610 powerpc/86xx: Enable VME driver on the GE PPC9A powerpc/86xx: Add MSI section to GE PPC9A DTS ...
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| Original file line number | Diff line number | Diff line change |
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| @@ -0,0 +1,70 @@ | ||
| MPC5121 PSC Device Tree Bindings | ||
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| PSC in UART mode | ||
| ---------------- | ||
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| For PSC in UART mode the needed PSC serial devices | ||
| are specified by fsl,mpc5121-psc-uart nodes in the | ||
| fsl,mpc5121-immr SoC node. Additionally the PSC FIFO | ||
| Controller node fsl,mpc5121-psc-fifo is requered there: | ||
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| fsl,mpc5121-psc-uart nodes | ||
| -------------------------- | ||
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| Required properties : | ||
| - compatible : Should contain "fsl,mpc5121-psc-uart" and "fsl,mpc5121-psc" | ||
| - cell-index : Index of the PSC in hardware | ||
| - reg : Offset and length of the register set for the PSC device | ||
| - interrupts : <a b> where a is the interrupt number of the | ||
| PSC FIFO Controller and b is a field that represents an | ||
| encoding of the sense and level information for the interrupt. | ||
| - interrupt-parent : the phandle for the interrupt controller that | ||
| services interrupts for this device. | ||
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| Recommended properties : | ||
| - fsl,rx-fifo-size : the size of the RX fifo slice (a multiple of 4) | ||
| - fsl,tx-fifo-size : the size of the TX fifo slice (a multiple of 4) | ||
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| fsl,mpc5121-psc-fifo node | ||
| ------------------------- | ||
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| Required properties : | ||
| - compatible : Should be "fsl,mpc5121-psc-fifo" | ||
| - reg : Offset and length of the register set for the PSC | ||
| FIFO Controller | ||
| - interrupts : <a b> where a is the interrupt number of the | ||
| PSC FIFO Controller and b is a field that represents an | ||
| encoding of the sense and level information for the interrupt. | ||
| - interrupt-parent : the phandle for the interrupt controller that | ||
| services interrupts for this device. | ||
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| Example for a board using PSC0 and PSC1 devices in serial mode: | ||
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| serial@11000 { | ||
| compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; | ||
| cell-index = <0>; | ||
| reg = <0x11000 0x100>; | ||
| interrupts = <40 0x8>; | ||
| interrupt-parent = < &ipic >; | ||
| fsl,rx-fifo-size = <16>; | ||
| fsl,tx-fifo-size = <16>; | ||
| }; | ||
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| serial@11100 { | ||
| compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; | ||
| cell-index = <1>; | ||
| reg = <0x11100 0x100>; | ||
| interrupts = <40 0x8>; | ||
| interrupt-parent = < &ipic >; | ||
| fsl,rx-fifo-size = <16>; | ||
| fsl,tx-fifo-size = <16>; | ||
| }; | ||
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| pscfifo@11f00 { | ||
| compatible = "fsl,mpc5121-psc-fifo"; | ||
| reg = <0x11f00 0x100>; | ||
| interrupts = <40 0x8>; | ||
| interrupt-parent = < &ipic >; | ||
| }; |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,134 @@ | ||
| GDB intends to support the following hardware debug features of BookE | ||
| processors: | ||
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| 4 hardware breakpoints (IAC) | ||
| 2 hardware watchpoints (read, write and read-write) (DAC) | ||
| 2 value conditions for the hardware watchpoints (DVC) | ||
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| For that, we need to extend ptrace so that GDB can query and set these | ||
| resources. Since we're extending, we're trying to create an interface | ||
| that's extendable and that covers both BookE and server processors, so | ||
| that GDB doesn't need to special-case each of them. We added the | ||
| following 3 new ptrace requests. | ||
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| 1. PTRACE_PPC_GETHWDEBUGINFO | ||
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| Query for GDB to discover the hardware debug features. The main info to | ||
| be returned here is the minimum alignment for the hardware watchpoints. | ||
| BookE processors don't have restrictions here, but server processors have | ||
| an 8-byte alignment restriction for hardware watchpoints. We'd like to avoid | ||
| adding special cases to GDB based on what it sees in AUXV. | ||
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| Since we're at it, we added other useful info that the kernel can return to | ||
| GDB: this query will return the number of hardware breakpoints, hardware | ||
| watchpoints and whether it supports a range of addresses and a condition. | ||
| The query will fill the following structure provided by the requesting process: | ||
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| struct ppc_debug_info { | ||
| unit32_t version; | ||
| unit32_t num_instruction_bps; | ||
| unit32_t num_data_bps; | ||
| unit32_t num_condition_regs; | ||
| unit32_t data_bp_alignment; | ||
| unit32_t sizeof_condition; /* size of the DVC register */ | ||
| uint64_t features; /* bitmask of the individual flags */ | ||
| }; | ||
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| features will have bits indicating whether there is support for: | ||
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| #define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x1 | ||
| #define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x2 | ||
| #define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x4 | ||
| #define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x8 | ||
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| 2. PTRACE_SETHWDEBUG | ||
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| Sets a hardware breakpoint or watchpoint, according to the provided structure: | ||
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| struct ppc_hw_breakpoint { | ||
| uint32_t version; | ||
| #define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x1 | ||
| #define PPC_BREAKPOINT_TRIGGER_READ 0x2 | ||
| #define PPC_BREAKPOINT_TRIGGER_WRITE 0x4 | ||
| uint32_t trigger_type; /* only some combinations allowed */ | ||
| #define PPC_BREAKPOINT_MODE_EXACT 0x0 | ||
| #define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x1 | ||
| #define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x2 | ||
| #define PPC_BREAKPOINT_MODE_MASK 0x3 | ||
| uint32_t addr_mode; /* address match mode */ | ||
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| #define PPC_BREAKPOINT_CONDITION_MODE 0x3 | ||
| #define PPC_BREAKPOINT_CONDITION_NONE 0x0 | ||
| #define PPC_BREAKPOINT_CONDITION_AND 0x1 | ||
| #define PPC_BREAKPOINT_CONDITION_EXACT 0x1 /* different name for the same thing as above */ | ||
| #define PPC_BREAKPOINT_CONDITION_OR 0x2 | ||
| #define PPC_BREAKPOINT_CONDITION_AND_OR 0x3 | ||
| #define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000 /* byte enable bits */ | ||
| #define PPC_BREAKPOINT_CONDITION_BE(n) (1<<((n)+16)) | ||
| uint32_t condition_mode; /* break/watchpoint condition flags */ | ||
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| uint64_t addr; | ||
| uint64_t addr2; | ||
| uint64_t condition_value; | ||
| }; | ||
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| A request specifies one event, not necessarily just one register to be set. | ||
| For instance, if the request is for a watchpoint with a condition, both the | ||
| DAC and DVC registers will be set in the same request. | ||
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| With this GDB can ask for all kinds of hardware breakpoints and watchpoints | ||
| that the BookE supports. COMEFROM breakpoints available in server processors | ||
| are not contemplated, but that is out of the scope of this work. | ||
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| ptrace will return an integer (handle) uniquely identifying the breakpoint or | ||
| watchpoint just created. This integer will be used in the PTRACE_DELHWDEBUG | ||
| request to ask for its removal. Return -ENOSPC if the requested breakpoint | ||
| can't be allocated on the registers. | ||
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| Some examples of using the structure to: | ||
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| - set a breakpoint in the first breakpoint register | ||
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| p.version = PPC_DEBUG_CURRENT_VERSION; | ||
| p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE; | ||
| p.addr_mode = PPC_BREAKPOINT_MODE_EXACT; | ||
| p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; | ||
| p.addr = (uint64_t) address; | ||
| p.addr2 = 0; | ||
| p.condition_value = 0; | ||
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| - set a watchpoint which triggers on reads in the second watchpoint register | ||
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| p.version = PPC_DEBUG_CURRENT_VERSION; | ||
| p.trigger_type = PPC_BREAKPOINT_TRIGGER_READ; | ||
| p.addr_mode = PPC_BREAKPOINT_MODE_EXACT; | ||
| p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; | ||
| p.addr = (uint64_t) address; | ||
| p.addr2 = 0; | ||
| p.condition_value = 0; | ||
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| - set a watchpoint which triggers only with a specific value | ||
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| p.version = PPC_DEBUG_CURRENT_VERSION; | ||
| p.trigger_type = PPC_BREAKPOINT_TRIGGER_READ; | ||
| p.addr_mode = PPC_BREAKPOINT_MODE_EXACT; | ||
| p.condition_mode = PPC_BREAKPOINT_CONDITION_AND | PPC_BREAKPOINT_CONDITION_BE_ALL; | ||
| p.addr = (uint64_t) address; | ||
| p.addr2 = 0; | ||
| p.condition_value = (uint64_t) condition; | ||
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| - set a ranged hardware breakpoint | ||
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| p.version = PPC_DEBUG_CURRENT_VERSION; | ||
| p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE; | ||
| p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE; | ||
| p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; | ||
| p.addr = (uint64_t) begin_range; | ||
| p.addr2 = (uint64_t) end_range; | ||
| p.condition_value = 0; | ||
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| 3. PTRACE_DELHWDEBUG | ||
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| Takes an integer which identifies an existing breakpoint or watchpoint | ||
| (i.e., the value returned from PTRACE_SETHWDEBUG), and deletes the | ||
| corresponding breakpoint or watchpoint.. |
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