---

yaml
---
r: 348063
b: refs/heads/master
c: 5ddf4d4
h: refs/heads/master
i:
  348061: f353019
  348059: d9ca91f
  348055: c67a3b1
  348047: 0b90eda
  348031: 80cbe9e
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 3d8ec277394ee0cf9fdd5a411017c3b4f1b0aff2
+refs/heads/master: 5ddf4d4a543dd3303b20d7e9a4b3549589c5f095

trunk/drivers/gpu/drm/nouveau/core/include/subdev/bios/init.h

@@ -13,6 +13,7 @@ struct nvbios_init {
 	u32 nested;
 	u16 repeat;
 	u16 repend;
+	u32 ramcfg;
 };
 
 int nvbios_exec(struct nvbios_init *);

trunk/drivers/gpu/drm/nouveau/core/subdev/bios/init.c

@@ -410,10 +410,26 @@ init_ram_restrict_group_count(struct nvbios_init *init)
 	return 0x00;
 }
 
+static u8
+init_ram_restrict_strap(struct nvbios_init *init)
+{
+	/* This appears to be the behaviour of the VBIOS parser, and *is*
+	 * important to cache the NV_PEXTDEV_BOOT0 on later chipsets to
+	 * avoid fucking up the memory controller (somehow) by reading it
+	 * on every INIT_RAM_RESTRICT_ZM_GROUP opcode.
+	 *
+	 * Preserving the non-caching behaviour on earlier chipsets just
+	 * in case *not* re-reading the strap causes similar breakage.
+	 */
+	if (!init->ramcfg || init->bios->version.major < 0x70)
+		init->ramcfg = init_rd32(init, 0x101000);
+	return (init->ramcfg & 0x00000003c) >> 2;
+}
+
 static u8
 init_ram_restrict(struct nvbios_init *init)
 {
-	u32 strap = (init_rd32(init, 0x101000) & 0x0000003c) >> 2;
+	u8  strap = init_ram_restrict_strap(init);
 	u16 table = init_ram_restrict_table(init);
 	if (table)
 		return nv_ro08(init->bios, table + strap);