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[POWERPC] ipic: add new interrupts introduced by new chip
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These interrupts are introduced by the latest Freescale SoC
such as MPC837x.

Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Li Yang authored and Kumar Gala committed Dec 11, 2007
1 parent a58d524 commit f03ca95
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Showing 3 changed files with 143 additions and 14 deletions.
138 changes: 133 additions & 5 deletions arch/powerpc/sysdev/ipic.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -33,6 +33,30 @@ static struct ipic * primary_ipic;
static DEFINE_SPINLOCK(ipic_lock);

static struct ipic_info ipic_info[] = {
[1] = {
.pend = IPIC_SIPNR_H,
.mask = IPIC_SIMSR_H,
.prio = IPIC_SIPRR_C,
.force = IPIC_SIFCR_H,
.bit = 16,
.prio_mask = 0,
},
[2] = {
.pend = IPIC_SIPNR_H,
.mask = IPIC_SIMSR_H,
.prio = IPIC_SIPRR_C,
.force = IPIC_SIFCR_H,
.bit = 17,
.prio_mask = 1,
},
[4] = {
.pend = IPIC_SIPNR_H,
.mask = IPIC_SIMSR_H,
.prio = IPIC_SIPRR_C,
.force = IPIC_SIFCR_H,
.bit = 19,
.prio_mask = 3,
},
[9] = {
.pend = IPIC_SIPNR_H,
.mask = IPIC_SIMSR_H,
Expand All @@ -57,6 +81,22 @@ static struct ipic_info ipic_info[] = {
.bit = 26,
.prio_mask = 2,
},
[12] = {
.pend = IPIC_SIPNR_H,
.mask = IPIC_SIMSR_H,
.prio = IPIC_SIPRR_D,
.force = IPIC_SIFCR_H,
.bit = 27,
.prio_mask = 3,
},
[13] = {
.pend = IPIC_SIPNR_H,
.mask = IPIC_SIMSR_H,
.prio = IPIC_SIPRR_D,
.force = IPIC_SIFCR_H,
.bit = 28,
.prio_mask = 4,
},
[14] = {
.pend = IPIC_SIPNR_H,
.mask = IPIC_SIMSR_H,
Expand Down Expand Up @@ -201,6 +241,46 @@ static struct ipic_info ipic_info[] = {
.bit = 7,
.prio_mask = 7,
},
[42] = {
.pend = IPIC_SIPNR_H,
.mask = IPIC_SIMSR_H,
.prio = IPIC_SIPRR_B,
.force = IPIC_SIFCR_H,
.bit = 10,
.prio_mask = 2,
},
[44] = {
.pend = IPIC_SIPNR_H,
.mask = IPIC_SIMSR_H,
.prio = IPIC_SIPRR_B,
.force = IPIC_SIFCR_H,
.bit = 12,
.prio_mask = 4,
},
[45] = {
.pend = IPIC_SIPNR_H,
.mask = IPIC_SIMSR_H,
.prio = IPIC_SIPRR_B,
.force = IPIC_SIFCR_H,
.bit = 13,
.prio_mask = 5,
},
[46] = {
.pend = IPIC_SIPNR_H,
.mask = IPIC_SIMSR_H,
.prio = IPIC_SIPRR_B,
.force = IPIC_SIFCR_H,
.bit = 14,
.prio_mask = 6,
},
[47] = {
.pend = IPIC_SIPNR_H,
.mask = IPIC_SIMSR_H,
.prio = IPIC_SIPRR_B,
.force = IPIC_SIFCR_H,
.bit = 15,
.prio_mask = 7,
},
[48] = {
.pend = IPIC_SEPNR,
.mask = IPIC_SEMSR,
Expand Down Expand Up @@ -336,6 +416,20 @@ static struct ipic_info ipic_info[] = {
.force = IPIC_SIFCR_L,
.bit = 16,
},
[81] = {
.pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L,
.prio = 0,
.force = IPIC_SIFCR_L,
.bit = 17,
},
[82] = {
.pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L,
.prio = 0,
.force = IPIC_SIFCR_L,
.bit = 18,
},
[84] = {
.pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L,
Expand All @@ -350,6 +444,34 @@ static struct ipic_info ipic_info[] = {
.force = IPIC_SIFCR_L,
.bit = 21,
},
[86] = {
.pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L,
.prio = 0,
.force = IPIC_SIFCR_L,
.bit = 22,
},
[87] = {
.pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L,
.prio = 0,
.force = IPIC_SIFCR_L,
.bit = 23,
},
[88] = {
.pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L,
.prio = 0,
.force = IPIC_SIFCR_L,
.bit = 24,
},
[89] = {
.pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L,
.prio = 0,
.force = IPIC_SIFCR_L,
.bit = 25,
},
[90] = {
.pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L,
Expand Down Expand Up @@ -593,14 +715,18 @@ struct ipic * __init ipic_init(struct device_node *node, unsigned int flags)
* configure SICFR accordingly */
if (flags & IPIC_SPREADMODE_GRP_A)
temp |= SICFR_IPSA;
if (flags & IPIC_SPREADMODE_GRP_B)
temp |= SICFR_IPSB;
if (flags & IPIC_SPREADMODE_GRP_C)
temp |= SICFR_IPSC;
if (flags & IPIC_SPREADMODE_GRP_D)
temp |= SICFR_IPSD;
if (flags & IPIC_SPREADMODE_MIX_A)
temp |= SICFR_MPSA;
if (flags & IPIC_SPREADMODE_MIX_B)
temp |= SICFR_MPSB;

ipic_write(ipic->regs, IPIC_SICNR, temp);
ipic_write(ipic->regs, IPIC_SICFR, temp);

/* handle MCP route */
temp = 0;
Expand Down Expand Up @@ -672,10 +798,12 @@ void ipic_set_highest_priority(unsigned int virq)

void ipic_set_default_priority(void)
{
ipic_write(primary_ipic->regs, IPIC_SIPRR_A, IPIC_SIPRR_A_DEFAULT);
ipic_write(primary_ipic->regs, IPIC_SIPRR_D, IPIC_SIPRR_D_DEFAULT);
ipic_write(primary_ipic->regs, IPIC_SMPRR_A, IPIC_SMPRR_A_DEFAULT);
ipic_write(primary_ipic->regs, IPIC_SMPRR_B, IPIC_SMPRR_B_DEFAULT);
ipic_write(primary_ipic->regs, IPIC_SIPRR_A, IPIC_PRIORITY_DEFAULT);
ipic_write(primary_ipic->regs, IPIC_SIPRR_B, IPIC_PRIORITY_DEFAULT);
ipic_write(primary_ipic->regs, IPIC_SIPRR_C, IPIC_PRIORITY_DEFAULT);
ipic_write(primary_ipic->regs, IPIC_SIPRR_D, IPIC_PRIORITY_DEFAULT);
ipic_write(primary_ipic->regs, IPIC_SMPRR_A, IPIC_PRIORITY_DEFAULT);
ipic_write(primary_ipic->regs, IPIC_SMPRR_B, IPIC_PRIORITY_DEFAULT);
}

void ipic_enable_mcp(enum ipic_mcp_irq mcp_irq)
Expand Down
7 changes: 3 additions & 4 deletions arch/powerpc/sysdev/ipic.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -23,13 +23,12 @@
#define IPIC_IRQ_EXT7 23

/* Default Priority Registers */
#define IPIC_SIPRR_A_DEFAULT 0x05309770
#define IPIC_SIPRR_D_DEFAULT 0x05309770
#define IPIC_SMPRR_A_DEFAULT 0x05309770
#define IPIC_SMPRR_B_DEFAULT 0x05309770
#define IPIC_PRIORITY_DEFAULT 0x05309770

/* System Global Interrupt Configuration Register */
#define SICFR_IPSA 0x00010000
#define SICFR_IPSB 0x00020000
#define SICFR_IPSC 0x00040000
#define SICFR_IPSD 0x00080000
#define SICFR_MPSA 0x00200000
#define SICFR_MPSB 0x00400000
Expand Down
12 changes: 7 additions & 5 deletions include/asm-powerpc/ipic.h
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Original file line number Diff line number Diff line change
Expand Up @@ -20,11 +20,13 @@

/* Flags when we init the IPIC */
#define IPIC_SPREADMODE_GRP_A 0x00000001
#define IPIC_SPREADMODE_GRP_D 0x00000002
#define IPIC_SPREADMODE_MIX_A 0x00000004
#define IPIC_SPREADMODE_MIX_B 0x00000008
#define IPIC_DISABLE_MCP_OUT 0x00000010
#define IPIC_IRQ0_MCP 0x00000020
#define IPIC_SPREADMODE_GRP_B 0x00000002
#define IPIC_SPREADMODE_GRP_C 0x00000004
#define IPIC_SPREADMODE_GRP_D 0x00000008
#define IPIC_SPREADMODE_MIX_A 0x00000010
#define IPIC_SPREADMODE_MIX_B 0x00000020
#define IPIC_DISABLE_MCP_OUT 0x00000040
#define IPIC_IRQ0_MCP 0x00000080

/* IPIC registers offsets */
#define IPIC_SICFR 0x00 /* System Global Interrupt Configuration Register */
Expand Down

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