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ASoC: intel: Fix SSP port configuration after RTD3 resume.
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Currently the SSP port settings are being clobbered as part of the DSP
RTD3 restore logic. make sure we save the correct params and restore them
at resume. The FW sadly does not save SSP settings as part of the PM
context.

Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
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Liam Girdwood authored and Mark Brown committed Sep 9, 2015
1 parent d770e55 commit f1ec5ec
Showing 1 changed file with 12 additions and 8 deletions.
20 changes: 12 additions & 8 deletions sound/soc/intel/haswell/sst-haswell-ipc.c
Original file line number Diff line number Diff line change
Expand Up @@ -302,6 +302,10 @@ struct sst_hsw {
struct sst_hsw_ipc_dx_reply dx;
void *dx_context;
dma_addr_t dx_context_paddr;
enum sst_hsw_device_id dx_dev;
enum sst_hsw_device_mclk dx_mclk;
enum sst_hsw_device_mode dx_mode;
u32 dx_clock_divider;

/* boot */
wait_queue_head_t boot_wait;
Expand Down Expand Up @@ -1400,10 +1404,10 @@ int sst_hsw_device_set_config(struct sst_hsw *hsw,

trace_ipc_request("set device config", dev);

config.ssp_interface = dev;
config.clock_frequency = mclk;
config.mode = mode;
config.clock_divider = clock_divider;
hsw->dx_dev = config.ssp_interface = dev;
hsw->dx_mclk = config.clock_frequency = mclk;
hsw->dx_mode = config.mode = mode;
hsw->dx_clock_divider = config.clock_divider = clock_divider;
if (mode == SST_HSW_DEVICE_TDM_CLOCK_MASTER)
config.channels = 4;
else
Expand Down Expand Up @@ -1704,10 +1708,10 @@ int sst_hsw_dsp_runtime_resume(struct sst_hsw *hsw)
return -EIO;
}

/* Set ADSP SSP port settings */
ret = sst_hsw_device_set_config(hsw, SST_HSW_DEVICE_SSP_0,
SST_HSW_DEVICE_MCLK_FREQ_24_MHZ,
SST_HSW_DEVICE_CLOCK_MASTER, 9);
/* Set ADSP SSP port settings - sadly the FW does not store SSP port
settings as part of the PM context. */
ret = sst_hsw_device_set_config(hsw, hsw->dx_dev, hsw->dx_mclk,
hsw->dx_mode, hsw->dx_clock_divider);
if (ret < 0)
dev_err(dev, "error: SSP re-initialization failed\n");

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