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yaml
---
r: 335497
b: refs/heads/master
c: f7c5b3d
h: refs/heads/master
i:
  335495: a08a0e7
v: v3
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Vipul Kumar Samar authored and Linus Walleij committed Nov 5, 2012
1 parent 3e1c6ba commit f4d4815
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Showing 2 changed files with 52 additions and 43 deletions.
2 changes: 1 addition & 1 deletion [refs]
Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: 82a2deb93cb2237e3a91db6d0317571ecbd6e531
refs/heads/master: f7c5b3d574a036e401b8ccf7ee93b873561c09e4
93 changes: 51 additions & 42 deletions trunk/drivers/pinctrl/spear/pinctrl-spear1310.c
Original file line number Diff line number Diff line change
Expand Up @@ -1763,29 +1763,52 @@ static struct spear_function can1_function = {
.ngroups = ARRAY_SIZE(can1_grps),
};

/* Pad multiplexing for pci device */
static const unsigned pci_sata_pins[] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 18,
/* Pad multiplexing for (ras-ip) pci device */
static const unsigned pci_pins[] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 18,
19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36,
37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54,
55, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99 };
#define PCI_SATA_MUXREG \
{ \
.reg = PAD_FUNCTION_EN_0, \
.mask = PMX_MCI_DATA8_15_MASK, \
.val = 0, \
}, { \
.reg = PAD_FUNCTION_EN_1, \
.mask = PMX_PCI_REG1_MASK, \
.val = 0, \
}, { \
.reg = PAD_FUNCTION_EN_2, \
.mask = PMX_PCI_REG2_MASK, \
.val = 0, \
}

/* pad multiplexing for pcie0 device */
static struct spear_muxreg pci_muxreg[] = {
{
.reg = PAD_FUNCTION_EN_0,
.mask = PMX_MCI_DATA8_15_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_1,
.mask = PMX_PCI_REG1_MASK,
.val = 0,
}, {
.reg = PAD_FUNCTION_EN_2,
.mask = PMX_PCI_REG2_MASK,
.val = 0,
},
};

static struct spear_modemux pci_modemux[] = {
{
.muxregs = pci_muxreg,
.nmuxregs = ARRAY_SIZE(pci_muxreg),
},
};

static struct spear_pingroup pci_pingroup = {
.name = "pci_grp",
.pins = pci_pins,
.npins = ARRAY_SIZE(pci_pins),
.modemuxs = pci_modemux,
.nmodemuxs = ARRAY_SIZE(pci_modemux),
};

static const char *const pci_grps[] = { "pci_grp" };
static struct spear_function pci_function = {
.name = "pci",
.groups = pci_grps,
.ngroups = ARRAY_SIZE(pci_grps),
};

/* pad multiplexing for (fix-part) pcie0 device */
static struct spear_muxreg pcie0_muxreg[] = {
PCI_SATA_MUXREG,
{
.reg = PCIE_SATA_CFG,
.mask = PCIE_CFG_VAL(0),
Expand All @@ -1802,15 +1825,12 @@ static struct spear_modemux pcie0_modemux[] = {

static struct spear_pingroup pcie0_pingroup = {
.name = "pcie0_grp",
.pins = pci_sata_pins,
.npins = ARRAY_SIZE(pci_sata_pins),
.modemuxs = pcie0_modemux,
.nmodemuxs = ARRAY_SIZE(pcie0_modemux),
};

/* pad multiplexing for pcie1 device */
/* pad multiplexing for (fix-part) pcie1 device */
static struct spear_muxreg pcie1_muxreg[] = {
PCI_SATA_MUXREG,
{
.reg = PCIE_SATA_CFG,
.mask = PCIE_CFG_VAL(1),
Expand All @@ -1827,15 +1847,12 @@ static struct spear_modemux pcie1_modemux[] = {

static struct spear_pingroup pcie1_pingroup = {
.name = "pcie1_grp",
.pins = pci_sata_pins,
.npins = ARRAY_SIZE(pci_sata_pins),
.modemuxs = pcie1_modemux,
.nmodemuxs = ARRAY_SIZE(pcie1_modemux),
};

/* pad multiplexing for pcie2 device */
/* pad multiplexing for (fix-part) pcie2 device */
static struct spear_muxreg pcie2_muxreg[] = {
PCI_SATA_MUXREG,
{
.reg = PCIE_SATA_CFG,
.mask = PCIE_CFG_VAL(2),
Expand All @@ -1852,22 +1869,20 @@ static struct spear_modemux pcie2_modemux[] = {

static struct spear_pingroup pcie2_pingroup = {
.name = "pcie2_grp",
.pins = pci_sata_pins,
.npins = ARRAY_SIZE(pci_sata_pins),
.modemuxs = pcie2_modemux,
.nmodemuxs = ARRAY_SIZE(pcie2_modemux),
};

static const char *const pci_grps[] = { "pcie0_grp", "pcie1_grp", "pcie2_grp" };
static struct spear_function pci_function = {
.name = "pci",
.groups = pci_grps,
.ngroups = ARRAY_SIZE(pci_grps),
static const char *const pcie_grps[] = { "pcie0_grp", "pcie1_grp", "pcie2_grp"
};
static struct spear_function pcie_function = {
.name = "pci_express",
.groups = pcie_grps,
.ngroups = ARRAY_SIZE(pcie_grps),
};

/* pad multiplexing for sata0 device */
static struct spear_muxreg sata0_muxreg[] = {
PCI_SATA_MUXREG,
{
.reg = PCIE_SATA_CFG,
.mask = SATA_CFG_VAL(0),
Expand All @@ -1884,15 +1899,12 @@ static struct spear_modemux sata0_modemux[] = {

static struct spear_pingroup sata0_pingroup = {
.name = "sata0_grp",
.pins = pci_sata_pins,
.npins = ARRAY_SIZE(pci_sata_pins),
.modemuxs = sata0_modemux,
.nmodemuxs = ARRAY_SIZE(sata0_modemux),
};

/* pad multiplexing for sata1 device */
static struct spear_muxreg sata1_muxreg[] = {
PCI_SATA_MUXREG,
{
.reg = PCIE_SATA_CFG,
.mask = SATA_CFG_VAL(1),
Expand All @@ -1909,15 +1921,12 @@ static struct spear_modemux sata1_modemux[] = {

static struct spear_pingroup sata1_pingroup = {
.name = "sata1_grp",
.pins = pci_sata_pins,
.npins = ARRAY_SIZE(pci_sata_pins),
.modemuxs = sata1_modemux,
.nmodemuxs = ARRAY_SIZE(sata1_modemux),
};

/* pad multiplexing for sata2 device */
static struct spear_muxreg sata2_muxreg[] = {
PCI_SATA_MUXREG,
{
.reg = PCIE_SATA_CFG,
.mask = SATA_CFG_VAL(2),
Expand All @@ -1934,8 +1943,6 @@ static struct spear_modemux sata2_modemux[] = {

static struct spear_pingroup sata2_pingroup = {
.name = "sata2_grp",
.pins = pci_sata_pins,
.npins = ARRAY_SIZE(pci_sata_pins),
.modemuxs = sata2_modemux,
.nmodemuxs = ARRAY_SIZE(sata2_modemux),
};
Expand Down Expand Up @@ -2093,6 +2100,7 @@ static struct spear_pingroup *spear1310_pingroups[] = {
&can0_dis_sd_pingroup,
&can1_dis_sd_pingroup,
&can1_dis_kbd_pingroup,
&pci_pingroup,
&pcie0_pingroup,
&pcie1_pingroup,
&pcie2_pingroup,
Expand Down Expand Up @@ -2138,6 +2146,7 @@ static struct spear_function *spear1310_functions[] = {
&can0_function,
&can1_function,
&pci_function,
&pcie_function,
&sata_function,
&ssp1_function,
&gpt64_function,
Expand Down

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