---

yaml
---
r: 184660
b: refs/heads/master
c: e80a972
h: refs/heads/master
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: d3730192294c1c98b17a67aadbbdc4c28ad05c6e
+refs/heads/master: e80a9729b15f4c2c00ed51d61aa543fb4269d5ca

trunk/arch/arm/mach-omap2/clock.h

@@ -47,7 +47,6 @@
 #define DPLL_LOW_POWER_BYPASS	0x5
 #define DPLL_LOCKED		0x7
 
-int omap2_clk_init(void);
 int omap2_clk_enable(struct clk *clk);
 void omap2_clk_disable(struct clk *clk);
 long omap2_clk_round_rate(struct clk *clk, unsigned long rate);

trunk/arch/arm/mach-omap2/clock2xxx.h

@@ -19,6 +19,7 @@ unsigned long omap2xxx_clk_get_core_rate(struct clk *clk);
 u32 omap2xxx_get_apll_clkin(void);
 u32 omap2xxx_get_sysclkdiv(void);
 void omap2xxx_clk_prepare_for_reboot(void);
+int omap2xxx_clk_init(void);
 
 /* REVISIT: These should be set dynamically for CONFIG_MULTI_OMAP2 */
 #ifdef CONFIG_ARCH_OMAP2420

trunk/arch/arm/mach-omap2/clock2xxx_data.c

@@ -2238,7 +2238,7 @@ static struct omap_clk omap24xx_clks[] = {
  * init code
  */
 
-int __init omap2_clk_init(void)
+int __init omap2xxx_clk_init(void)
 {
 	const struct prcm_config *prcm;
 	struct omap_clk *c;

trunk/arch/arm/mach-omap2/clock34xx.c

@@ -150,7 +150,7 @@ int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
 	return omap3_noncore_dpll_set_rate(clk, rate);
 }
 
-void omap3_clk_lock_dpll5(void)
+void __init omap3_clk_lock_dpll5(void)
 {
 	struct clk *dpll5_clk;
 	struct clk *dpll5_m2_clk;

trunk/arch/arm/mach-omap2/clock34xx.h

@@ -8,6 +8,7 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_34XX_H
 #define __ARCH_ARM_MACH_OMAP2_CLOCK_34XX_H
 
+int omap3xxx_clk_init(void);
 int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate);
 int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate);
 void omap3_clk_lock_dpll5(void);

trunk/arch/arm/mach-omap2/clock34xx_data.c

@@ -3212,11 +3212,9 @@ static struct omap_clk omap3xxx_clks[] = {
 };
 
 
-int __init omap2_clk_init(void)
+int __init omap3xxx_clk_init(void)
 {
-	/* struct prcm_config *prcm; */
 	struct omap_clk *c;
-	/* u32 clkrate; */
 	u32 cpu_clkflg = CK_3XXX;
 
 	if (cpu_is_omap3517()) {
@@ -3254,21 +3252,6 @@ int __init omap2_clk_init(void)
 			omap2_init_clk_clkdm(c->lk.clk);
 		}
 
-	/* REVISIT: Not yet ready for OMAP3 */
-#if 0
-	/* Check the MPU rate set by bootloader */
-	clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
-	for (prcm = rate_table; prcm->mpu_speed; prcm++) {
-		if (!(prcm->flags & cpu_mask))
-			continue;
-		if (prcm->xtal_speed != sys_ck.rate)
-			continue;
-		if (prcm->dpll_speed <= clkrate)
-			break;
-	}
-	curr_prcm_set = prcm;
-#endif
-
 	recalculate_root_clocks();
 
 	printk(KERN_INFO "Clocking rate (Crystal/Core/MPU): "

trunk/arch/arm/mach-omap2/clock44xx.h

@@ -10,6 +10,8 @@
 #define OMAP4430_MAX_DPLL_MULT	2048
 #define OMAP4430_MAX_DPLL_DIV	128
 
+int omap4xxx_clk_init(void);
+
 extern const struct clkops clkops_noncore_dpll_ops;
 
 #endif

trunk/arch/arm/mach-omap2/clock44xx_data.c

@@ -2726,11 +2726,9 @@ static struct omap_clk omap44xx_clks[] = {
 	CLK(NULL,	"utmi_p2_gfclk_ck",		&utmi_p2_gfclk_ck,	CK_443X),
 };
 
-int __init omap2_clk_init(void)
+int __init omap4xxx_clk_init(void)
 {
-	/* struct prcm_config *prcm; */
 	struct omap_clk *c;
-	/* u32 clkrate; */
 	u32 cpu_clkflg;
 
 	if (cpu_is_omap44xx()) {

trunk/arch/arm/mach-omap2/io.c

@@ -35,7 +35,9 @@
 #include <plat/serial.h>
 #include <plat/vram.h>
 
-#include "clock.h"
+#include "clock2xxx.h"
+#include "clock34xx.h"
+#include "clock44xx.h"
 
 #include <plat/omap-pm.h>
 #include <plat/powerdomain.h>
@@ -320,7 +322,16 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
 	omap2_mux_init();
 	omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps);
 #endif
-	omap2_clk_init();
+
+	if (cpu_is_omap24xx())
+		omap2xxx_clk_init();
+	else if (cpu_is_omap34xx())
+		omap3xxx_clk_init();
+	else if (cpu_is_omap44xx())
+		omap4xxx_clk_init();
+	else
+		pr_err("Could not init clock framework - unknown CPU\n");
+
 	omap_serial_early_init();
 #ifndef CONFIG_ARCH_OMAP4
 	omap_hwmod_late_init();