---

yaml
---
r: 181225
b: refs/heads/master
c: 7be85c6
h: refs/heads/master
i:
  181223: f14cb84
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 0a5f337ecd20e70e84a5cfc0f2c24d0366087026
+refs/heads/master: 7be85c6eb4462cd973e680d9dcf897a7b5b26165

trunk/arch/sh/include/asm/clock.h

@@ -148,6 +148,7 @@ int sh_clk_mstp32_register(struct clk *clks, int nr);
 
 struct clk_div4_table {
 	struct clk_div_mult_table *div_mult_table;
+	void (*kick)(struct clk *clk);
 };
 
 int sh_clk_div4_register(struct clk *clks, int nr,

trunk/arch/sh/kernel/cpu/clock-cpg.c

@@ -188,6 +188,7 @@ static int sh_clk_div4_set_parent(struct clk *clk, struct clk *parent)
 
 static int sh_clk_div4_set_rate(struct clk *clk, unsigned long rate, int algo_id)
 {
+	struct clk_div4_table *d4t = clk->priv;
 	unsigned long value;
 	int idx = clk_rate_table_find(clk, clk->freq_table, rate);
 	if (idx < 0)
@@ -198,6 +199,9 @@ static int sh_clk_div4_set_rate(struct clk *clk, unsigned long rate, int algo_id
 	value |= (idx << clk->enable_bit);
 	__raw_writel(value, clk->enable_reg);
 
+	if (d4t->kick)
+		d4t->kick(clk);
+
 	return 0;
 }
 

trunk/arch/sh/kernel/cpu/sh4a/clock-sh7724.c

@@ -127,6 +127,16 @@ struct clk *main_clks[] = {
 	&div3_clk,
 };
 
+static void div4_kick(struct clk *clk)
+{
+	unsigned long value;
+
+	/* set KICK bit in FRQCRA to update hardware setting */
+	value = __raw_readl(FRQCRA);
+	value |= (1 << 31);
+	__raw_writel(value, FRQCRA);
+}
+
 static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 0, 24, 32, 36, 48, 0, 72 };
 
 static struct clk_div_mult_table div4_div_mult_table = {
@@ -136,6 +146,7 @@ static struct clk_div_mult_table div4_div_mult_table = {
 
 static struct clk_div4_table div4_table = {
 	.div_mult_table = &div4_div_mult_table,
+	.kick = div4_kick,
 };
 
 enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR };