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Merge tag 'iommu-updates-v3.9' of git://git.kernel.org/pub/scm/linux/…
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…kernel/git/joro/iommu

Pull IOMMU Updates from Joerg Roedel:
 "Besides some fixes and cleanups in the code there are three more
  important changes to point out this time:

	* New IOMMU driver for the ARM SHMOBILE platform
	* An IOMMU-API extension for non-paging IOMMUs (required for
	  upcoming PAMU driver)
	* Rework of the way the Tegra IOMMU driver accesses its
	  registetrs - register windows are easier to extend now.

  There are also a few changes to non-iommu code, but that is acked by
  the respective maintainers."

* tag 'iommu-updates-v3.9' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (23 commits)
  iommu/tegra: assume CONFIG_OF in SMMU driver
  iommu/tegra: assume CONFIG_OF in gart driver
  iommu/amd: Remove redundant NULL check before dma_ops_domain_free().
  iommu/amd: Initialize device table after dma_ops
  iommu/vt-d: Zero out allocated memory in dmar_enable_qi
  iommu/tegra: smmu: Fix incorrect mask for regbase
  iommu/exynos: Make exynos_sysmmu_disable static
  ARM: mach-shmobile: r8a7740: Add IPMMU device
  ARM: mach-shmobile: sh73a0: Add IPMMU device
  ARM: mach-shmobile: sh7372: Add IPMMU device
  iommu/shmobile: Add iommu driver for Renesas IPMMU modules
  iommu: Add DOMAIN_ATTR_WINDOWS domain attribute
  iommu: Add domain window handling functions
  iommu: Implement DOMAIN_ATTR_PAGING attribute
  iommu: Check for valid pgsize_bitmap in iommu_map/unmap
  iommu: Make sure DOMAIN_ATTR_MAX is really the maximum
  iommu/tegra: smmu: Change SMMU's dependency on ARCH_TEGRA
  iommu/tegra: smmu: Use helper function to check for valid register offset
  iommu/tegra: smmu: Support variable MMIO ranges/blocks
  iommu/tegra: Add missing spinlock initialization
  ...
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Linus Torvalds committed Feb 26, 2013
2 parents 42a0a1b + 604542b commit f6c0ffa
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Showing 28 changed files with 1,043 additions and 462 deletions.
5 changes: 0 additions & 5 deletions arch/arm/mach-exynos/Kconfig
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Expand Up @@ -105,11 +105,6 @@ config EXYNOS4_SETUP_FIMD0
help
Common setup code for FIMD0.

config EXYNOS_DEV_SYSMMU
bool
help
Common setup code for SYSTEM MMU in EXYNOS platforms

config EXYNOS4_DEV_USB_OHCI
bool
help
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1 change: 0 additions & 1 deletion arch/arm/mach-exynos/Makefile
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Expand Up @@ -52,7 +52,6 @@ obj-$(CONFIG_ARCH_EXYNOS4) += dev-audio.o
obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o
obj-$(CONFIG_EXYNOS_DEV_DMA) += dma.o
obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI) += dev-ohci.o
obj-$(CONFIG_EXYNOS_DEV_SYSMMU) += dev-sysmmu.o

obj-$(CONFIG_ARCH_EXYNOS) += setup-i2c0.o
obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o
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41 changes: 20 additions & 21 deletions arch/arm/mach-exynos/clock-exynos4.c
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Expand Up @@ -24,7 +24,6 @@

#include <mach/map.h>
#include <mach/regs-clock.h>
#include <mach/sysmmu.h>

#include "common.h"
#include "clock-exynos4.h"
Expand Down Expand Up @@ -709,53 +708,53 @@ static struct clk exynos4_init_clocks_off[] = {
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 14),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
.name = "sysmmu",
.devname = "exynos-sysmmu.0",
.enable = exynos4_clk_ip_mfc_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(mfc_r, 1),
.name = "sysmmu",
.devname = "exynos-sysmmu.1",
.enable = exynos4_clk_ip_mfc_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(tv, 2),
.name = "sysmmu",
.devname = "exynos-sysmmu.2",
.enable = exynos4_clk_ip_tv_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(jpeg, 3),
.name = "sysmmu",
.devname = "exynos-sysmmu.3",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 11),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(rot, 4),
.name = "sysmmu",
.devname = "exynos-sysmmu.4",
.enable = exynos4_clk_ip_image_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(fimc0, 5),
.name = "sysmmu",
.devname = "exynos-sysmmu.5",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(fimc1, 6),
.name = "sysmmu",
.devname = "exynos-sysmmu.6",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(fimc2, 7),
.name = "sysmmu",
.devname = "exynos-sysmmu.7",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 9),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(fimc3, 8),
.name = "sysmmu",
.devname = "exynos-sysmmu.8",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 10),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(fimd0, 10),
.name = "sysmmu",
.devname = "exynos-sysmmu.10",
.enable = exynos4_clk_ip_lcd0_ctrl,
.ctrlbit = (1 << 4),
}
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9 changes: 4 additions & 5 deletions arch/arm/mach-exynos/clock-exynos4210.c
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Expand Up @@ -26,7 +26,6 @@
#include <mach/hardware.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include <mach/sysmmu.h>

#include "common.h"
#include "clock-exynos4.h"
Expand Down Expand Up @@ -129,13 +128,13 @@ static struct clk init_clocks_off[] = {
.enable = exynos4_clk_ip_lcd1_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(2d, 14),
.name = "sysmmu",
.devname = "exynos-sysmmu.9",
.enable = exynos4_clk_ip_image_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(fimd1, 11),
.name = "sysmmu",
.devname = "exynos-sysmmu.11",
.enable = exynos4_clk_ip_lcd1_ctrl,
.ctrlbit = (1 << 4),
}, {
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23 changes: 16 additions & 7 deletions arch/arm/mach-exynos/clock-exynos4212.c
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Expand Up @@ -26,7 +26,6 @@
#include <mach/hardware.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include <mach/sysmmu.h>

#include "common.h"
#include "clock-exynos4.h"
Expand Down Expand Up @@ -111,20 +110,30 @@ static struct clksrc_clk clksrcs[] = {

static struct clk init_clocks_off[] = {
{
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(2d, 14),
.name = "sysmmu",
.devname = "exynos-sysmmu.9",
.enable = exynos4_clk_ip_dmc_ctrl,
.ctrlbit = (1 << 24),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(isp, 9),
.name = "sysmmu",
.devname = "exynos-sysmmu.12",
.enable = exynos4212_clk_ip_isp0_ctrl,
.ctrlbit = (7 << 8),
}, {
.name = SYSMMU_CLOCK_NAME2,
.devname = SYSMMU_CLOCK_DEVNAME(isp, 9),
.name = "sysmmu",
.devname = "exynos-sysmmu.13",
.enable = exynos4212_clk_ip_isp1_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.14",
.enable = exynos4212_clk_ip_isp0_ctrl,
.ctrlbit = (1 << 11),
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.15",
.enable = exynos4212_clk_ip_isp0_ctrl,
.ctrlbit = (1 << 12),
}, {
.name = "flite",
.devname = "exynos-fimc-lite.0",
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62 changes: 33 additions & 29 deletions arch/arm/mach-exynos/clock-exynos5.c
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Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,6 @@

#include <mach/map.h>
#include <mach/regs-clock.h>
#include <mach/sysmmu.h>

#include "common.h"

Expand Down Expand Up @@ -859,73 +858,78 @@ static struct clk exynos5_init_clocks_off[] = {
.enable = exynos5_clk_ip_gscl_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
.name = "sysmmu",
.devname = "exynos-sysmmu.1",
.enable = &exynos5_clk_ip_mfc_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(mfc_r, 1),
.name = "sysmmu",
.devname = "exynos-sysmmu.0",
.enable = &exynos5_clk_ip_mfc_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(tv, 2),
.name = "sysmmu",
.devname = "exynos-sysmmu.2",
.enable = &exynos5_clk_ip_disp1_ctrl,
.ctrlbit = (1 << 9)
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(jpeg, 3),
.name = "sysmmu",
.devname = "exynos-sysmmu.3",
.enable = &exynos5_clk_ip_gen_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(rot, 4),
.name = "sysmmu",
.devname = "exynos-sysmmu.4",
.enable = &exynos5_clk_ip_gen_ctrl,
.ctrlbit = (1 << 6)
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(gsc0, 5),
.name = "sysmmu",
.devname = "exynos-sysmmu.5",
.enable = &exynos5_clk_ip_gscl_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(gsc1, 6),
.name = "sysmmu",
.devname = "exynos-sysmmu.6",
.enable = &exynos5_clk_ip_gscl_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(gsc2, 7),
.name = "sysmmu",
.devname = "exynos-sysmmu.7",
.enable = &exynos5_clk_ip_gscl_ctrl,
.ctrlbit = (1 << 9),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(gsc3, 8),
.name = "sysmmu",
.devname = "exynos-sysmmu.8",
.enable = &exynos5_clk_ip_gscl_ctrl,
.ctrlbit = (1 << 10),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(isp, 9),
.name = "sysmmu",
.devname = "exynos-sysmmu.9",
.enable = &exynos5_clk_ip_isp0_ctrl,
.ctrlbit = (0x3F << 8),
}, {
.name = SYSMMU_CLOCK_NAME2,
.devname = SYSMMU_CLOCK_DEVNAME(isp, 9),
.name = "sysmmu",
.devname = "exynos-sysmmu.10",
.enable = &exynos5_clk_ip_isp1_ctrl,
.ctrlbit = (0xF << 4),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(camif0, 12),
.name = "sysmmu",
.devname = "exynos-sysmmu.11",
.enable = &exynos5_clk_ip_disp1_ctrl,
.ctrlbit = (1 << 8)
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.12",
.enable = &exynos5_clk_ip_gscl_ctrl,
.ctrlbit = (1 << 11),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(camif1, 13),
.name = "sysmmu",
.devname = "exynos-sysmmu.13",
.enable = &exynos5_clk_ip_gscl_ctrl,
.ctrlbit = (1 << 12),
}, {
.name = SYSMMU_CLOCK_NAME,
.devname = SYSMMU_CLOCK_DEVNAME(2d, 14),
.name = "sysmmu",
.devname = "exynos-sysmmu.14",
.enable = &exynos5_clk_ip_acp_ctrl,
.ctrlbit = (1 << 7)
}
Expand Down
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