---

yaml
---
r: 127171
b: refs/heads/master
c: cbe7dd6
h: refs/heads/master
i:
  127169: 60d83d1
  127167: d4851ba
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 9e234faf98ec4fbcc3292d767df2c709a032cba5
+refs/heads/master: cbe7dd699e0bdda85a9279f2659b51b92e6782e3

trunk/drivers/ieee1394/ohci1394.c

@@ -3199,15 +3199,16 @@ static int __devinit ohci1394_pci_probe(struct pci_dev *dev,
 	/* Now enable LPS, which we need in order to start accessing
 	 * most of the registers.  In fact, on some cards (ALI M5251),
 	 * accessing registers in the SClk domain without LPS enabled
-	 * will lock up the machine.  Wait 50msec to make sure we have
-	 * full link enabled.  */
+	 * will lock up the machine. */
 	reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_LPS);
 
 	/* Disable and clear interrupts */
 	reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff);
 	reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff);
 
-	mdelay(50);
+	/* Flush MMIO writes and wait to make sure we have full link enabled. */
+	reg_read(ohci, OHCI1394_Version);
+	msleep(50);
 
 	/* Determine the number of available IR and IT contexts. */
 	ohci->nb_iso_rcv_ctx =
@@ -3422,7 +3423,8 @@ static int ohci1394_pci_resume(struct pci_dev *dev)
 	reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_LPS);
 	reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff);
 	reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff);
-	mdelay(50);
+	reg_read(ohci, OHCI1394_Version);
+	msleep(50);
 
 	err = request_irq(dev->irq, ohci_irq_handler, IRQF_SHARED,
 			  OHCI1394_DRIVER_NAME, ohci);