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ARM: rockchip: move shared dt properties to common source file
The rk3188 SoC shares a lot of peripherals with the rk3066 SoC, but not all. Therefore move the common parts to a shared dtsi. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Heiko Stuebner
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Oct 14, 2013
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| /* | ||
| * Copyright (c) 2013 MundoReader S.L. | ||
| * Author: Heiko Stuebner <heiko@sntech.de> | ||
| * | ||
| * This program is free software; you can redistribute it and/or modify | ||
| * it under the terms of the GNU General Public License as published by | ||
| * the Free Software Foundation; either version 2 of the License, or | ||
| * (at your option) any later version. | ||
| * | ||
| * This program is distributed in the hope that it will be useful, | ||
| * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| * GNU General Public License for more details. | ||
| */ | ||
|
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| #include <dt-bindings/interrupt-controller/irq.h> | ||
| #include <dt-bindings/interrupt-controller/arm-gic.h> | ||
| #include "skeleton.dtsi" | ||
|
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||
| / { | ||
| interrupt-parent = <&gic>; | ||
|
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| soc { | ||
| #address-cells = <1>; | ||
| #size-cells = <1>; | ||
| compatible = "simple-bus"; | ||
| ranges; | ||
|
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| gic: interrupt-controller@1013d000 { | ||
| compatible = "arm,cortex-a9-gic"; | ||
| interrupt-controller; | ||
| #interrupt-cells = <3>; | ||
| reg = <0x1013d000 0x1000>, | ||
| <0x1013c100 0x0100>; | ||
| }; | ||
|
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||
| L2: l2-cache-controller@10138000 { | ||
| compatible = "arm,pl310-cache"; | ||
| reg = <0x10138000 0x1000>; | ||
| cache-unified; | ||
| cache-level = <2>; | ||
| }; | ||
|
|
||
| local-timer@1013c600 { | ||
| compatible = "arm,cortex-a9-twd-timer"; | ||
| reg = <0x1013c600 0x20>; | ||
| interrupts = <GIC_PPI 13 0x304>; | ||
| clocks = <&dummy150m>; | ||
| }; | ||
|
|
||
| uart0: serial@10124000 { | ||
| compatible = "snps,dw-apb-uart"; | ||
| reg = <0x10124000 0x400>; | ||
| interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; | ||
| reg-shift = <2>; | ||
| reg-io-width = <1>; | ||
| clocks = <&clk_gates1 8>; | ||
| status = "disabled"; | ||
| }; | ||
|
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||
| uart1: serial@10126000 { | ||
| compatible = "snps,dw-apb-uart"; | ||
| reg = <0x10126000 0x400>; | ||
| interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; | ||
| reg-shift = <2>; | ||
| reg-io-width = <1>; | ||
| clocks = <&clk_gates1 10>; | ||
| status = "disabled"; | ||
| }; | ||
|
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||
| uart2: serial@20064000 { | ||
| compatible = "snps,dw-apb-uart"; | ||
| reg = <0x20064000 0x400>; | ||
| interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; | ||
| reg-shift = <2>; | ||
| reg-io-width = <1>; | ||
| clocks = <&clk_gates1 12>; | ||
| status = "disabled"; | ||
| }; | ||
|
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||
| uart3: serial@20068000 { | ||
| compatible = "snps,dw-apb-uart"; | ||
| reg = <0x20068000 0x400>; | ||
| interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; | ||
| reg-shift = <2>; | ||
| reg-io-width = <1>; | ||
| clocks = <&clk_gates1 14>; | ||
| status = "disabled"; | ||
| }; | ||
|
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| dwmmc@10214000 { | ||
| compatible = "rockchip,rk2928-dw-mshc"; | ||
| reg = <0x10214000 0x1000>; | ||
| interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
|
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| clocks = <&clk_gates5 10>, <&clk_gates2 11>; | ||
| clock-names = "biu", "ciu"; | ||
|
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| status = "disabled"; | ||
| }; | ||
|
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| dwmmc@10218000 { | ||
| compatible = "rockchip,rk2928-dw-mshc"; | ||
| reg = <0x10218000 0x1000>; | ||
| interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
|
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| clocks = <&clk_gates5 11>, <&clk_gates2 13>; | ||
| clock-names = "biu", "ciu"; | ||
|
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| status = "disabled"; | ||
| }; | ||
| }; | ||
| }; |